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Sat, 01 Aug 2026 10:31:42 -0700 (PDT) X-Received: by 2002:a17:90b:580d:b0:37f:9ce1:735e with SMTP id 98e67ed59e1d1-38fbc4e6e79mr4079107a91.31.1785605501803; Sat, 01 Aug 2026 10:31:41 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13fab4e44bcsm21865553c88.12.2026.08.01.10.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Aug 2026 10:31:41 -0700 (PDT) From: Taniya Das Date: Sat, 01 Aug 2026 23:01:17 +0530 Subject: [PATCH 1/2] clk: qcom: gpucc-glymur: Mark the GPU CX GDSC as votable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260801-kaanapali-gpu-voteable-v1-1-fe804d24d2e9@oss.qualcomm.com> References: <20260801-kaanapali-gpu-voteable-v1-0-fe804d24d2e9@oss.qualcomm.com> In-Reply-To: <20260801-kaanapali-gpu-voteable-v1-0-fe804d24d2e9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Ajit Pandey , Imran Shaik , Jagadeesh Kona , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Info: AW1haW4tMjYwODAxMDE0MSBTYWx0ZWRfX0QdxxQ0eiKQF Ut2DJU9AfAmA/cKQ3aNY07ZsjBU0ZpsYUhPqj8O3pONrIEaS1UGjQPhVDxZmzZh1OsX3JFStGW/ L0a5j6S+CfXp5oG+ozEh5GiCGB9vo84= X-Proofpoint-GUID: U2mTFNsTH176tJAodwBN8rDze79JNhMl X-Authority-Analysis: v=2.4 cv=Gu5yPE1C c=1 sm=1 tr=0 ts=6a6e2d7e cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=jRw_QlPnGipwSP_GHmoA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: U2mTFNsTH176tJAodwBN8rDze79JNhMl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAxMDE0MSBTYWx0ZWRfXxaGJ20SdlvPh 1bE00rwL4WoUISyydS7tQopUYPEJvMkRiZGhgan0S+v5e1W20GpLTYTLXrmBpEMTKrOeZoNK6FC aBBnuxj7rQLbyUGyyw0XWEmdX42jipTxY7W8KaY2njTHVoJHbXjqnJfL5wx7E+MdWpOpzd4/hYV UZAtvF4jOcjUwuYv9Q9IklfvVv04Z3kynkWFYxQPoI07Yb5xrZ0Izt68jBXGqiq7dVAF8ClQtSV nqH3orip7g6AQbgjzmrSge91bUNwsztRTcZX51GwdxUzGn24Ti+LoyKb0l4Bv5TPDSxNa7wGDiv 7n3FgJRD1FMXbjWCRCqzFkHcrKxDlupKm06xRfCymFDNC9csEnJKsj8YmkRlcGyME5TOnp38q2O 5R363930+n/j5dI1n4K/S7QAu5o/5AITjtU3pFQgrsjvGv0E1HyCb8byQlvL+EYYtY/qYUS+4Nr /j6MKpaZdI512wRAD2g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-01_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608010141 The GPU CX GDSC on Glymur is a votable power domain and hence should not be polled for power-off status during GDSC disable. Also, its power-on status should be read from the GDS hardware control register. Accommodate this by removing POLL_CFG_GDSCR and adding the VOTABLE flag for the GPU CX GDSC, similar to other platforms (e.g. SM8750 and Milos). Fixes: 67e645285dd0 ("clk: qcom: Add support for GPUCC and GXCLK for Glymur") Signed-off-by: Taniya Das --- drivers/clk/qcom/gpucc-glymur.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-glymur.c b/drivers/clk/qcom/gpucc-glymur.c index 001b2454786a0c0d63370b3ff385ed5a2bff1b07..cac51de20b2950733d6d48ceb14e60d6181665ab 100644 --- a/drivers/clk/qcom/gpucc-glymur.c +++ b/drivers/clk/qcom/gpucc-glymur.c @@ -510,7 +510,7 @@ static struct gdsc gpu_cc_cx_gdsc = { .name = "gpu_cc_cx_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = RETAIN_FF_ENABLE | VOTABLE, }; static struct clk_regmap *gpu_cc_glymur_clocks[] = { -- 2.34.1