From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B22B3CB2E7 for ; Sun, 2 Aug 2026 16:53:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689625; cv=none; b=kPyZX1irSPXu8/dDR5+MGwnnoO79YFLdZqTUl6UjsS4Elf+YIqCZJ7WQ9FBkzxNVQgGd4InDSx8aHJ0lL/rDWM3McgjqEeBYRXGeVs3p/jgmcZIMcnTFBFFn+0rOS4AhgiSNuln9S3v+QOxZ5Y0btn/8cDw7ONxszCUJohgEl0w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689625; c=relaxed/simple; bh=d59v2ypClbCc8c5Hd0Ef1c4VRvvmQVeQAL6wALV2raY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oS0nQQpOTsPeJUFkVC0TxHbrxn9Nq3itYboBd9bsLCb/eQ7Im3J2bsf1xQCcTMgwCthR1FK+ouc6cGDraf6FYG6mD+10oPPO5HdvUr/wgsr2vRmN6urFxU5KoF24qA+H7U/zcAS+vgBc23hPWUyHwyUSjTor1A7lJty3Kylno4M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jd1MSEcN; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jd1MSEcN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 402DC1F00ADE; Sun, 2 Aug 2026 16:53:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785689623; bh=KbS6tAMDWYU94iLSiqDXxb03HkeRPSt0gzD9443d824=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=jd1MSEcN/ND/t2vB7gQSkN/B2k2z8ChAMwJrvoVaABc/BZrrWZBMNRnYJ7SW1Gi7O DizMAR3jJqLHVyKn1rc16gE08VuEWeBMuTq3a2Jb+i89BC5rjvzJSAl9ugKUuxE3Uc WelHoACDYW8QFPLMuq4LF1sGpY3pbun0AtFtkJlUl8UIQ7jmEWatEdKMtc6zZcgfrn GgDIkrSemPXw2h993BMcKdRnEwbjxtsERjfL3dYRvpJGvZ24EBdwA4btAxtejsMuDc vUqRp4tQIBOwrS9MUhW1BSwib2bLPZEJ91o7ldyxEWFPOYLyMD6yPShwdmlXEB8ubF fTJ+Jm+gZZEjQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wqZRV-0000000BVIZ-16iI; Sun, 02 Aug 2026 16:53:41 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v3 6/8] clocksource/drivers/arm_arch_timer: Add command-line control over the counter errata management Date: Sun, 2 Aug 2026 17:53:25 +0100 Message-ID: <20260802165327.385217-7-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260802165327.385217-1-maz@kernel.org> References: <20260802165327.385217-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false While we now have a safe way to use "fast" accessors once all CPUs have booted, this leaves people booting with maxcpus= on non-broken hardware stuck with the "slow" counter accessors. Give these people a way out by adding a new command-line parameter aptly named clocksource.arm_arch_timer.cnt_errata, which allows the user to promise that no erratum handling is required for the counters by setting this value to 0. Warnings will be emitted if the user has over-promised. Suggested-by; Will Deacon Signed-off-by: Marc Zyngier --- Documentation/admin-guide/kernel-parameters.txt | 13 +++++++++++++ drivers/clocksource/arm_arch_timer.c | 17 ++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index b5493a7f8f228..f0e6534269c2b 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -830,6 +830,19 @@ Kernel parameters loops can be debugged more effectively on production systems. + clocksource.arm_arch_timer.cnt_errata= + [ARM64,EARLY] + Format: + Enable/disable the counter errata management. + Enabling it switches over to fast accessors once it is + known that no CPU requires any workaround while reading + the counters. + Disabling it will bypass workarounds when reading the + counters, even if not all the CPUs have been probed. + Warnings will be produced if the need for a workaround + is detected. + Default is enabled. + clocksource.verify_n_cpus= [KNL] Limit the number of CPUs checked for clocksources marked with CLOCK_SOURCE_VERIFY_PERCPU that diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 747f51d9225c2..b3b31d4f4815f 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -500,8 +500,10 @@ void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa per_cpu(timer_unstable_counter_workaround, i) = wa; } - if (wa->read_cntvct_el0 || wa->read_cntpct_el0) + if (wa->read_cntvct_el0 || wa->read_cntpct_el0) { + WARN_ON_ONCE(!arch_counter_broken_accessors()); atomic_set(&timer_unstable_counter_workaround_in_use, 1); + } /* * Don't use the vdso fastpath if errata require using the @@ -597,12 +599,22 @@ static void arch_timer_set_direct_accessors(void) if (!arch_timer_counter_has_wa()) schedule_work(&enable_accessors_wk); } + +static bool cnt_errata_config __initdata = true; + +static int __init early_cnt_errata(char *buf) +{ + return kstrtobool(buf, &cnt_errata_config); +} +early_param("clocksource.arm_arch_timer.cnt_errata", early_cnt_errata); #else #define arch_timer_check_ool_workaround(t,a) do { } while(0) #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) #define arch_timer_counter_has_wa() ({false;}) static inline bool arch_counter_broken_accessors(void) { return false ; } #define arch_timer_set_direct_accessors() do { } while(0) +#define enable_direct_accessors(w) do { } while(0) +#define cnt_errata_config false #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ static __always_inline irqreturn_t timer_handler(const int access, @@ -955,6 +967,9 @@ static void __init arch_counter_register(void) u64 start_count; int width; + if (!cnt_errata_config) + enable_direct_accessors(NULL); + switch (arch_timer_uses_ppi) { case ARCH_TIMER_PHYS_SECURE_PPI: case ARCH_TIMER_PHYS_NONSECURE_PPI: -- 2.47.3