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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:05 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Olivier Moysan , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 10/16] arm64: dts: st: add sai1 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:05 +0200 Message-ID: <20260803074224.3821911-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the sai1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi Reviewed-by: Olivier Moysan --- Changes in v7: - Add Reviewed-by tag of Olivier Moysan arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 695c9d771853..002fbc724b9d 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -520,6 +520,51 @@ pins { }; }; + /omit-if-no-ref/ + sai1a_pins_a: sai1a-0 { + pins1 { + pinmux = , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + ; /* SAI1_SCK_A */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SAI1_MCLK_A */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + /omit-if-no-ref/ + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux = , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + , /* SAI1_SCK_A */ + ; /* SAI1_MCLK_A */ + }; + }; + + /omit-if-no-ref/ + sai1b_pins_a: sai1b-0 { + pins { + pinmux = ; /* SAI1_SD_B */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + sai1b_sleep_pins_a: sai1b-sleep-0 { + pins { + pinmux = ; /* SAI1_SD_B */ + }; + }; + /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { -- 2.43.0