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[59.127.145.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39085f5c9a5sm1696416a91.15.2026.08.06.08.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 08:23:58 -0700 (PDT) From: Zhi-Jun You To: hujy652@gmail.com, Felix Fietkau , Lorenzo Bianconi Cc: andrew+netdev@lunn.ch, angelogioacchino.delregno@collabora.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, netdev@vger.kernel.org, pabeni@redhat.com, sujuan.chen@mediatek.com Subject: Re: [PATCH net v3 1/2] net: ethernet: mtk_wed: skip ring reset in wdma_tx_ring_setup for WED v3 Date: Thu, 6 Aug 2026 23:23:50 +0800 Message-ID: <20260806152350.555-1-hujy652@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260724172040.1653-1-hujy652@gmail.com> References: <20260724172040.1653-1-hujy652@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Mutt-References: <20260724172040.1653-1-hujy652@gmail.com> X-Mutt-Fcc: ~/sent Content-Transfer-Encoding: 8bit On Sat, Jul 25, 2026 at 01:20:39AM +0800, Zhi-Jun You wrote: > Currently WED v3 tx wdma ring, ring reset happens in a separate code > block unconditionally. > > Moreover, v3 has double the size of wdma_desc and has different init > values. mtk_wed_ring_reset doens't deal with that and would corrupt the > wdma_desc. > > Fix this by skipping mtk_wed_ring_reset in mtk_wdma_tx_ring_setup for > WED v3. Commenting on Sashiko's report: https://sashiko.dev/#/patchset/20260724172040.1653-1-hujy652%40gmail.com > > Fixes: e2f64db13aa1 ("net: ethernet: mtk_wed: introduce WED support for MT7988") > Signed-off-by: Zhi-Jun You > --- > Changes in v3: > - new patch addressing WED v3 ring reset issue raised by Sashiko > - Link to the review: https://lore.kernel.org/netdev/20260630144831.1109-1-hujy652@gmail.com/ > --- > drivers/net/ethernet/mediatek/mtk_wed.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c > index 10d9beaae372..7d2775a97fa0 100644 > --- a/drivers/net/ethernet/mediatek/mtk_wed.c > +++ b/drivers/net/ethernet/mediatek/mtk_wed.c > @@ -1938,7 +1938,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size, > wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); > wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0); > > - if (reset) > + if (!mtk_wed_is_v3_or_greater(dev->hw) && reset) > mtk_wed_ring_reset(wdma, MTK_WED_WDMA_RING_SIZE, true); > > if (!idx) { -This is a pre-existing issue, but while reviewing the WDMA ring reset logic, I noticed what looks like reversed logic in mtk_wdma_rx_reset(): drivers/net/ethernet/mediatek/mtk_wed.c:mtk_wdma_rx_reset() { ... for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) { if (dev->rx_wdma[i].desc) continue; wdma_w32(dev, MTK_WDMA_RING_RX(i) + MTK_WED_RING_OFS_CPU_IDX, 0); } ... } Does the if (dev->rx_wdma[i].desc) continue; check skip the CPU_IDX reset for active rings? When a WDMA RX reset occurs (e.g., during recovery from a hang), the hardware index is reset to 0, but the CPU_IDX register won't be reset for active rings since they have a non-NULL desc. Could this desynchronize the driver and hardware, leading to a permanent stall of the WDMA RX rings and network traffic failure? - ACK I will add a patch addressing this. Best regards, Zhi-Jun > -- > 2.47.3 >