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charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/1WNTQ7CIBgFr9KwFkP5K3XlPYwLoJ8WY4uBSjRN7 y7UGNPlJG/mzShCcBDRoZpRgOSi82MGtquQ7fV4Bey6zIgSKklDFdaDFBzHrrcOK0Fa3nGhjAa UjUeAi3uttdP5y/FpbmCnkiiL3sXJh/d6l+qy+5XbTTnVmOBGSFUTBdy0+mi8n+5u3Fs/oNJO9 G8rwrY2zbYWAMKAkjVjW3tZlg+u72sy+AAAAA== X-Change-ID: 20260728-am654-sdhci-85094d458bae To: Adrian Hunter , Ulf Hansson , Faiz Abbas , Judith Mendez Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal EBERHARD , Thomas Petazzoni , Miquel Raynal , "Diogo Ivo (Schneider Electric)" , stable@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2403; i=diogo.ivo@bootlin.com; h=from:subject:message-id; bh=M0M5lKX2UIIlsM00QGrNbOWcO4tieupUNj/BRRfnFSw=; b=owEBbQKS/ZANAwAKAQa+fFtWXslFAcsmYgBqdbyGI24z46x60j3L4aDDWbXgtncz2EyIo85PM Dm5/1Ph/ieJAjMEAAEKAB0WIQTma35o1i1081e8B2UGvnxbVl7JRQUCanW8hgAKCRAGvnxbVl7J RWacEACTq64gfSu4iWyG4NWbgPUi5m07R9HZhwNQt61k+MTHmRECGKocPVGSZTVbTz8hKjzqSXO h0rlZiDKg38lW968cbuQvUOk3idGPdwOlHOg8d6JytV7JK9r4UeCHM+hCjCc0seFOfO6hvN2tvR VfqX1JdyqLrvM8tiCwz9gpOaHoH/WPSUzPSCblMQ7tZppe+uWasY8cYaKizkbFVpB8nW3Hna5rg Tltj21eTrgzmfBlabQW371Q9ethVXJvCR3d+V61mI09SpcZxCokBNAGJ9TAY9sVmRvKsRS1di1S qujozxhQstOAoOTnzrVQMtz5qPJDxGSXu1tnABqpVuBdlfV9anf2IWOEpbDyfk/9WhGQtLW+pJy jeFvcCesxdRbsV26Rp/x3XL8EXIqjuOUKb6M442MRnfGPzZ/bs6255sxlWq/wmw1XDt061+Oc9/ NoqpEJr75hF2rtONyhfRU8Va3/MQR13kZwDLy6zHmDZZoBMnucgdJpY8LcBE064V/vwAl3P/3pm YL4keFxjrl5XIhCPdJMRqSz4RJT/+qnR1CV1jv3Tn+PYCOg15mp3KCwxRKxcdTYn4Kc+2LCrUFU 6tAm6tacwJjfTkHGj9felesgkfyCjkzWTnhtCYgRkhEatxsGVYAUw2GPpEu8Lpe1Nc2w+XsqYRn fM06P7bUIOAdokA== X-Developer-Key: i=diogo.ivo@bootlin.com; a=openpgp; fpr=E66B7E68D62D74F357BC076506BE7C5B565EC945 X-Last-TLS-Session-Version: TLSv1.3 DDR50 mode is not required to support the tuning command CMD19 by the eMMC/SD specification, meaning that calibration may fail on cards that do not implement it. This series fixes four issues discovered when using such cards: - Patch 1 moves the tuning_loop counter from a persistent struct field to a local variable, preventing failed tuning attempts from depleting the retry budget across calls. - Patch 2 ensures the command/data line reset is always performed after tuning, even on failure, preventing stale data in the controller buffer. - Patch 3 clears the ITAPDLY enable and delay values on tuning failure so that leftover calibration values do not interfere with subsequent I/O. - Patch 4 falls back to the DT-provided itap delay value for DDR50 when tuning fails in this mode, making a best-effort attempt at a known-good delay being programmed. Together these changes make DDR50 functional on TI J721E SoCs with cards that lack CMD19 tuning support. This second version addresses all comments from Sashiko, which I found to be correct. Signed-off-by: Diogo Ivo (Schneider Electric) --- Changes in v3: - Collect R-b from Judith and A-b from Adrian - Add debug print when applying DT fallback values (Patch 4) - Link to v2: https://patch.msgid.link/20260803-am654-sdhci-v2-0-a5ee5be86133@bootlin.com Changes in v2: - Add new patch moving tuning_loop to a local variable (Patch 1) - Clear ITAPDLY array values alongside HW registers on tuning failure (Patch 3) - Save DT-provided itap delay values for DDR50 in dedicated variables to preserve them across tuning cycles (Patch 4) - Link to v1: https://patch.msgid.link/20260729-am654-sdhci-v1-0-7568108e4b9a@bootlin.com --- Diogo Ivo (Schneider Electric) (4): mmc: sdhci_am654: Move tuning_loop to local variable mmc: sdhci_am654: Reset command and data lines on failed tuning mmc: sdhci_am654: Clear ITAPDLY on tuning failure mmc: sdhci_am654: Fallback to DT-provided itap delay on DDR50 tuning failure drivers/mmc/host/sdhci_am654.c | 43 +++++++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 15 deletions(-) --- base-commit: f9a2394a23482bfd330911e9c8295b71724feacd change-id: 20260728-am654-sdhci-85094d458bae Best regards, -- Diogo Ivo