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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f5a3cad9dsm743785b3a.23.2026.08.07.02.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 02:51:19 -0700 (PDT) From: Qiang Yu Subject: [PATCH v9 0/6] Add QMP PCIe Multi-PHY support Date: Fri, 07 Aug 2026 02:51:09 -0700 Message-Id: <20260807-glymur_linkmode_0807-v9-0-dd1c7e236e29@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAI2qdWoC/yXM7QpAMBTG8VvR+UxtK4ZbkcQcHC+jDZHcu+Hj7 6nnf4FFQ2gh9S4wuJOlWTskvgeqK3WLAdXOIJiIWMxk0I7ntJliJD1Mc43FN0ohq5CLiPOSg7s uBhs6vmyW/7Zb1aNa3xbc9wNkoVhAeAAAAA== X-Change-ID: 20260807-glymur_linkmode_0807-727b512611a1 To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786096278; l=7505; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=fRskgt/l1zaOaCfvGYuKNUzaILMzSpnTzlyDqSFgiP8=; b=yQfXVxmRqNN2Y2xwloF2df3ORdRYyw9biWggiVlF4jPLvZEHoqQlQmHyqCknPr8XneO4k/XuZ KruLy9sR9ZhAnHzsIzjXO5FmickY6DMnqpgdSy6DynnnZC3mHzBdCL3 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=Rt/16imK c=1 sm=1 tr=0 ts=6a75aa99 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=JfrnYn6hAAAA:8 a=qMU6Vhuv4BxmAn6ANj0A:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=cvBusfyB2V15izCimMoJ:22 a=1CNFftbPRP8L7MoqJWF3:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA3NCBTYWx0ZWRfX8SbMsgpbmrp7 sAO1ZDHVxQ404B2G6RK26W3KZZ+2PNro8jFMbL20oE6FRhQSrB+eyCt0x/aIm2HtjNqbEczWwlx 5yz2Hpcga5W598cg/gV5cHNFpdbfhcx/gG0YYjo9VlzMh5yzxB6ymStODWrlGJchKuSrjliFJDv ZUdmp6HmyrTTP8JUZrWM7mWvNoW9aXNn3k8OSTrWjVokOEtiCYk/F/Dk3HujSgOyx83j+Xqd3lX 97se6eXwE5x7NDoJo4Qe/YT0uLYWmcrExiuSIiX+k8Ej1/X6Wh3Gh1f5GContZYUxqxrqW3o3dO HlDTyp+UdO/LU1eTqpWXMblOAUfvlz2Tz4FfCuxEw+xmTvO8RbPCN9q5y+HaTLNGC4eUwqUFy/K yr+AgdKVBCleJPcB+a0N4DPtrqvmgsYiGWiKix8i5rVvi36Ek4ULzvxAjtz98tOTLPrMotIrs66 T8cpyfTVCxydJ6xwfbw== X-Proofpoint-GUID: 1UqvF8XgYlfEsmgao4NT26L7U3BU4Fuq X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA3NCBTYWx0ZWRfX521x7vZTKLdL OGxMzYMjtxSXlXD0gwTWx49IcDQRm9OaxsjUqr0VNzENwAPWSLFVpjmUy9j/j6giXaJPb9gNkTb /ev8mPG7JXAothypkzCuQAxa0B2LaLs= X-Proofpoint-ORIG-GUID: 1UqvF8XgYlfEsmgao4NT26L7U3BU4Fuq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070074 Hi all, Some QMP PCIe PHY hardware blocks can be configured through a link-mode register into different link topologies, such as a single wide link, or multiple independent narrower links (e.g. x8 or x4+x4 mode on the Glymur PCIe3 PHY). Earlier revisions tried to extend the existing single-instance phy-qcom-qmp-pcie.c driver to cover this hardware. That added a large amount of conditional, multi-PHY logic to a driver whose data model assumes one PHY per node. This series adds a dedicated PHY provider driver, phy-qcom-qmp-pcie-multiphy.c: A single PHY provider node describes the shared hardware block. A new "qcom,link-mode" property points at the TCSR syscon register that reports the active topology; the driver reads it once at probe. #phy-cells = <1> lets consumers pass a logical PHY index to obtain their sub-PHY. Match data is indexed by link mode, and each link mode has its own array of per-PHY config tables, so one shared provider exposes a different set of logical PHYs depending on the active mode. The driver inherits the PHY settings and link mode already programmed by firmware, so only the no-CSR reset is used, and no PHY setting tables or related structures are defined. Each sub-PHY owns its register regions and power domain, so in a bifurcated mode the links are brought up, and powered independently. The driver is implemented and validated on Glymur, and is intended to be extensible to other multi-mode QMP PCIe PHYs. Thanks, Qiang Signed-off-by: Qiang Yu --- Changes in v9: - Drop the redundant default PHY_QCOM_QMP and fix minor style nits in the driver (Vinod). - Add reviewed-by tag. - Link to v8: https://lore.kernel.org/all/20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com/ Changes in v8: - driver: drop the always-true fixed_rate check, the impossible num_pipe_outputs < 0 fallback, and the unused pipe_clk_fixed field; collapse qmp_pcie_read_link_mode() to return regmap_read() directly. - glymur.dtsi: use GIC_SPI instead of a literal 0 in pcie3a interrupt-map. - Pick up Konrad's Reviewed-by on patches 2-5. - Link to v7: https://lore.kernel.org/all/20260724-glymur_linkmode_0724-v7-0-65c8469c6b65@oss.qualcomm.com/ Changes in v7: - Pick up Mani's Reviewed-by (driver), Ack (binding) and Krzysztof's Reviewed-by (binding). - binding: fix commit message to reference the actual filename. - driver: rename Kconfig title to "Multi PHY" and driver to qcom-qmp-pcie-multiphy; PHY_INIT_COMPLETE_TIMEOUT -> _US; - Print errno in error messages; reverse-xmas-tree probe locals; handle NULL power-domain with IS_ERR_OR_NULL()/-ENODATA. - glymur.dtsi: reword subject to adding PCIe3 PHY and PCIe3a controller nodes; node -> pcie@1c10000; drop num-lanes; add pciclass to pcie3a_port0; fix 32-bit MEM range identity mapping. - Link to v6: https://lore.kernel.org/all/20260722-glymur_linkmode_0722-v6-0-bba8156b8cbb@oss.qualcomm.com/ Changes in v6: - Remove dependency description since it was merged - Rename the binding to qcom,glymur-qmp-gen5x8-pcie-phy.yaml - Drop redundant minItems on reg, clocks, power-domains, and resets - Rename phy_a/phy_b reset-names and power-domain-names entries to port_a/port_b (port_a_nocsr/port_b_nocsr for the no-CSR resets) match reg-names. - Add a description for #phy-cells explaining the sub-PHY index meaning. - Drop the unused "pcie3_phy:" label from the binding example. - Drop the year from the driver's copyright header. - Fix a pm_runtime refcount imbalance on the qmp_pcie_pd_power_on() error path by switching to pm_runtime_resume_and_get(). - Split the DTS patch into a SoC-level patch and a board-level patch. - Add two patches for Mahua, which only has PCIe3b wired up and no shared Gen5x8 PHY block. - Link to v5: https://lore.kernel.org/all/20260717-glymur_linkmode_0717-v5-0-4f9e87a61463@oss.qualcomm.com/ Changes in v5: - Split the Glymur multi PHY binding out of the shared qcom,sc8280xp-qmp-pcie-phy.yaml into its own schema. - Reworked phy-qcom-qmp-pcie-multiphy.c into a standalone driver instead of extending phy-qcom-qmp-pcie.c with conditional multi-PHYlogic. - Dropped the "link mode value" cell from qcom,link-mode. - Removed the QMP_PHY_SELECTOR_0/1 dt-bindings macros. - Link to v4: https://lore.kernel.org/all/20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com/ Changes in v4: - Replaced the static bifurcation probe model with a link-mode architecture: the active topology (x8 or x4+x4) is selected via a new "qcom,link-mode" DT property and written to a TCSR register at power-on. This replaces v3 patches 4 and 5 with four new patches (driver refactor, secondary PHY clock/reset lists, link-mode probe infrastructure, and Glymur config). - Updated dt-bindings to describe "qcom,link-mode", #phy-cells = <1>, per-mode validation rules, and added a new header with QMP_PHY_SELECTOR_* and QMP_PCIE_GLYMUR_MODE_* macros. - Patches 2 and 3 (multiple power-domains, multiple nocsr resets) are unchanged from v3. - Link to v3: https://lore.kernel.org/r/20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com Changes in v3: - Add description of each power-domain. - Add 64bit prefetchable memory range required by some EPs eg. AI100 ultra. - Move PCIe3a after PCIe3b and move PCIe3a PHY before PCIe3b PHY. - Link to v2: https://lore.kernel.org/all/20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com/ Changes in v2: - Remove pd_list from qmp_pcie struct as it is not used in phy driver. - align clk-names on " - Link to v1: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com/ To: Vinod Koul To: Neil Armstrong To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Qiang Yu To: Manivannan Sadhasivam To: Philipp Zabel To: Bjorn Andersson To: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Qiang Yu (6): dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes arm64: dts: qcom: glymur-crd: Add PHY supplies for pcie3_phy arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy arm64: dts: qcom: mahua-crd: Add PHY supplies for pcie3b_phy .../phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml | 177 +++++ arch/arm64/boot/dts/qcom/glymur-crd.dts | 8 + arch/arm64/boot/dts/qcom/glymur.dtsi | 336 +++++++++- arch/arm64/boot/dts/qcom/mahua-crd.dts | 5 + arch/arm64/boot/dts/qcom/mahua.dtsi | 89 +++ drivers/phy/qualcomm/Kconfig | 10 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 743 +++++++++++++++++++++ 8 files changed, 1367 insertions(+), 2 deletions(-) --- base-commit: ea2bff00da89d7767d677bb68470130ba96f4928 change-id: 20260807-glymur_linkmode_0807-727b512611a1 Best regards, -- Qiang Yu