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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f5a3cad9dsm743785b3a.23.2026.08.07.02.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 02:51:21 -0700 (PDT) From: Qiang Yu Date: Fri, 07 Aug 2026 02:51:10 -0700 Subject: [PATCH v9 1/6] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260807-glymur_linkmode_0807-v9-1-dd1c7e236e29@oss.qualcomm.com> References: <20260807-glymur_linkmode_0807-v9-0-dd1c7e236e29@oss.qualcomm.com> In-Reply-To: <20260807-glymur_linkmode_0807-v9-0-dd1c7e236e29@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786096278; l=6637; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=jxxfUzpwxpcsF507GMs4HufzpqaCXog14p6kapOUu1k=; b=E8dY8N5uWjW+uPlM643rXPJ0bF28E3PgyBrktmNAwKSXJRAiFRHD9EfphZMBIvPqnsKTdUQFF cve1PZeI2yzAOCh4o0xmtPs572G998MQoPyOrPvy7RKH5xemeU8NK7X X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA3NCBTYWx0ZWRfX1azxhWqeGmsT 23zSQ5Ng5/pa6W4yD4TH5QAI6kxAfZlbKbK7ZFTAdRG1GY+FvWNcDWUXs335zpFbfJJHAZxgU4R Qr+vCAEvKNNWlEtqblJi9qqUoyar9itNE+ZKnBBOWEkFX8AZC8/49pjQbVkb7MibPFYlQ67x0WO K5n0HNi+pxjP2PwO0MnN3ai/5x3GbuPKkBc/s/pt3VDlBUUkz0nxGpm+LbxVnilcJx1gV3d9W3B UtAoD5u5VoKonXFyiZatnEUfmayyd4eSBm3pOwdi78Ld/5XsfOT01/Ngq+zqUJUJ69N0skBhjj9 IMR/v28Qxaai1cceIcFFKI7RgrniMt9EbHVX1jOcZIu8u5hwuP4n26gENZwX2OzFnlfSXi74Q5/ PO6QLujBXBGgsYCKeKSbzWZ0v/o2xLSVA7+0DhC7aE4vLZnUN0pItduCkPScOVZ2ovtBTrmJyum e9WN/Yq5rCDeBUGWMug== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA3NCBTYWx0ZWRfX/kwDJUBJuj/p 8+xbrViEZLsRDxZGoOvcu7t553eE3f20teptJIGBZ05UHT6CJE57g4YMK0hgMzM36pU2NsAxQA2 LTHubsL6AxKMugyAwKP/8Onhxqv6eeI= X-Proofpoint-ORIG-GUID: y5oom0b8COnB9rIXnJgraXN4DHbtMgNB X-Proofpoint-GUID: y5oom0b8COnB9rIXnJgraXN4DHbtMgNB X-Authority-Analysis: v=2.4 cv=e5Y2j6p/ c=1 sm=1 tr=0 ts=6a75aa9a cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=TIvzfnD_jG5d2KfScrEA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070074 Add qcom,glymur-qmp-gen5x8-pcie-phy.yaml as a standalone binding for the Glymur Gen5 PCIe PHY hardware block. This block supports two link modes, selected at runtime via a TCSR syscon register: 1. x8 - a single 8-lane PHY instance is exposed 2. x4+x4 - two independent 4-lane PHY instances are exposed Keep this as a separate schema from qcom,sc8280xp-qmp-pcie-phy.yaml rather than folding it into the shared compatible list there, since the two PHY instances active in x8 mode require twice as many clocks, resets, and power-domains as any other entry in that file, and adding Glymur-specific properties like qcom,link-mode and reg-names there would only apply to this one compatible. Document the required clocks, resets, and power-domains for both PHY instances, and use #phy-cells = <1>, where the cell value is the PHY index within the active link mode. Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qiang Yu --- .../phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml | 177 +++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml new file mode 100644 index 000000000000..759f7f979dc6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PCIe multiple link-mode PHY controller (PCIe, Glymur) + +maintainers: + - Qiang Yu + - Manivannan Sadhasivam + +description: | + The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the + PCIe3a/PCIe3b controllers. This block supports two link modes, selected + at runtime via a TCSR syscon register: + + 1. x8 - a single 8-lane PHY instance is exposed (PCIe3a only) + 2. x4+x4 - two independent 4-lane PHY instances are exposed (PCIe3a and + PCIe3b) + + The node always describes both PHY instances ("port a" and "port b"), + regardless of which link mode is active on the board. + +properties: + compatible: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + + reg: + maxItems: 2 + + reg-names: + items: + - const: port_a + - const: port_b + + clocks: + maxItems: 10 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: phy_b_aux + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: pipediv2_b + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: port_a + - const: port_b + + resets: + maxItems: 4 + + reset-names: + items: + - const: port_a + - const: port_a_nocsr + - const: port_b + - const: port_b_nocsr + + vdda-phy-supply: true + + vdda-pll-supply: true + + vdda-refgen0p9-supply: true + + vdda-refgen1p2-supply: true + + qcom,link-mode: + description: + Reference to a register in the TCSR syscon that reports the link + mode the PCIe PHY is currently configured for, either a single x8 + link or two independent x4 links. The link mode is programmed by + firmware before Linux boots; this property is only used to read + the active link mode, specified as a phandle to the syscon and + the register offset. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of link mode register + + "#clock-cells": + const: 1 + + clock-output-names: + items: + - description: Name of the PHY A pipe clock output. + - description: Name of the PHY B pipe clock output. + + "#phy-cells": + const: 1 + description: + The cell is the index of the sub-PHY within the active link + mode, e.g. on Glymur, 0 for "port a" and 1 for "port b" in + x4x4 mode, and only index 0 (the single wide PHY) is valid in + x8 mode. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - vdda-refgen0p9-supply + - vdda-refgen1p2-supply + - qcom,link-mode + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + phy@f00000 { + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg = <0x00f00000 0x10000>, <0x00f10000 0x10000>; + reg-names = "port_a", "port_b"; + + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "phy_b_aux", "cfg_ahb_b", "rchng_b", "pipe_b", + "pipediv2_b"; + + resets = <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "port_a", "port_a_nocsr", "port_b", "port_b_nocsr"; + + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + power-domain-names = "port_a", "port_b"; + + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l2c>; + + vdda-refgen0p9-supply = <&vreg_l3c>; + vdda-refgen1p2-supply = <&vreg_l2c>; + + qcom,link-mode = <&tcsr 0x5000>; + + #clock-cells = <1>; + clock-output-names = "pcie3a_pipe_clk", "pcie3b_pipe_clk"; + + #phy-cells = <1>; + }; -- 2.34.1