From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59C003019BA for ; Fri, 7 Aug 2026 18:17:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786126639; cv=none; b=FsYb0EmIRsDmZ9t0C/V9Z7VogtlcqwVU+GypORfUdZ+dtmhlGwcv9fn+5ECvZyx77CR4HPmBbs7OEcTlgWwatsytEO8JC8se1gUa28Ia+vtDiixplCVmvSgzUhsAUraCQFe+Bi1gpEs/LA4xGVGJfv7Ba/ZdnzUq+cQfKnDoGyg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786126639; c=relaxed/simple; bh=73OmjTSCcVR/hU29SHD8+thM3YVWysYt5KI3hDNNhe0=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=rAjHyFPCy8F3Dncntd0L5c6VYFJxWdpjFxYNaLXQrZjtCV1ZfCbmfHPF2Zkk5tty7fjOVIXxvZN8RiXH4qRmUPwSVcBZ6G+fxdx9rcHLRTR28n9xvVcdFtUpeoH1S/Ex21Qm3Y6xjpc1Dgbn6q2rroGnqWn1JXVNHg1CipgWNv8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Ztn6r2+f; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=IfGWiRRM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Ztn6r2+f"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="IfGWiRRM" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 677GOQFb1496399 for ; Fri, 7 Aug 2026 18:17:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:message-id:mime-version :subject:to; s=qcppdkim1; bh=mTHaDqPuYE0hc87S0Qdk1xSBSfV/vLCUnN9 +GLT39n0=; b=Ztn6r2+fHEdxxJidlueemU/H3tuB3y5qDexALM31F4qZRnFgReE wgIBRUhn17QkSRg2nf70wxMYFRH44a9OKnv40IgGPYRLgIu3LsHSjHVTzSaDwc9a IeincXYpq5hgP4NZAJpdgY2Sl4I3yI+5qqFVU1H+ktaiJB96GI1LwSnBZvCQ/Eva +WixgyVVLfTsUkNCy4tNbgHMbo+yB9+bMuXEnWrgWT+QvE0WPFJ8u2TkU6zjqbR+ oP+LxE4PEWI6pSNzhDhQAH9Ravw2Zj6HvVl66W6t6E0qfH2/9J765E1GCa1bsJth oKtpicsSA1XtVxkEetwMAo3YepwSsYY/wFg== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fwctpa3mw-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 07 Aug 2026 18:17:16 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-51c0408254aso26166091cf.0 for ; Fri, 07 Aug 2026 11:17:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1786126636; x=1786731436; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to:content-type; bh=mTHaDqPuYE0hc87S0Qdk1xSBSfV/vLCUnN9+GLT39n0=; b=IfGWiRRMMp6v8ANL40KKETnG65n7XsxrNTSeeX9kwZDJa0GYtcrCLyMOwGOPIcOeFi M74vcJBXBv+cFPBDRPq8IZfi1Sthk0eektWP9NYQWNXTrIzVMlg83hhy5RfEMZjUAEBh ONfBrfVaieJdG5dqjD+WkB6a8VxR55tYNA3nI+JJtGPz2rJVwQVhShiSsFwEDnuMAv5M 04urWt4Brj/ZbEks9Wpf0VJFF+lrDNPHx/lSvnh08ZtJK4p7uCeExgASvnzF6EnRjhMm mFGYHQ8TnLmIl6EzpxImGcPRnNEn4HOLxZlp0+VvXiTay8h2887wbt8GALyk5OaNPVp5 w1bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786126636; x=1786731436; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=mTHaDqPuYE0hc87S0Qdk1xSBSfV/vLCUnN9+GLT39n0=; b=qpkEAo7L15/zXFnlH8BvakDES5rYQbqh8X4hIlx8d2c1UTSHvLvMSeFEfrqZg4ySoS qPiV08A6aoer+2krKIDtRtkQtbdoKQsh4v4HcE2U99JCz4MhoVzddfbfYgEUMk2hG7ck A2fLWzGYNuiN0GLKNgfaRuZL2hahy60qViZTmP/w5NUgXF1VDGrZWNI03dnEPAQAmmTg YrVj5Iq9UYZw9VooOeKYWocHev1RSWfN72WItv6Z+ZeeCTz8SDS40qTqTKvQcCAnRpbB S8/76TGAjG4D6yD2HnIo9GXBdw9XKX/96Gk9EU37YEG027VGv3BcCCcv2B6DTROw0wCG Uz2A== X-Gm-Message-State: AOJu0YzOYbqKtyRKjEEQ7JVMErbl+yPo7bh1HRcUrt/7EFE9IRw72dAX kDWC0X4MQCTsvLJE9qRhwi1ogvT+D5gbkP/q78nAb5a2oLnKgr9J8ql4N2/dMbyLCdnFeUtyNqH YZwy5ymxtyZruJfi2J5J2Eb0QtOAd6UjwawMOhoFTUy4FJu++qEmLAm2hPMWSNGuCekU= X-Gm-Gg: AR+sD12MNwdC64Az83QwOidRUF3tvpNykTYbXWs13YHfmjQ4Qo7h9PG+tSfrg5ouBvs kdlbqSid6Awi179S4Wj1aQ7t/ptN649ghsxvZN94WNxms30iIjTLe2cVKns78d9suzWZTxIkkCL xsqOzQnK1dsidfFB5IvvWkjGHDsFNophGavpdbR4w09MIMRC1ggOqP3Ctu6uxkpS7qpM7Q2okYD 4+4RA8yiWN9ZajnvOWTKfCkkJ2Eo2krb5stGd6eXvn1J0sDjR8oBfJOEu5li25WYyRsEckP3AlF rTi2oVlk5W/dfVH8Qe9eWIZ5HFTxjNdUhTz8RuA521ewu+J8lvIKdk+j/PabJ72syxg5/W0FoYh asrNIZjatZLKW0xRILlqVl6RbqGLJ7Rdi9OfSb1g= X-Received: by 2002:ac8:5c83:0:b0:517:63df:91a5 with SMTP id d75a77b69052e-52d2380c1b0mr7887471cf.19.1786126636432; Fri, 07 Aug 2026 11:17:16 -0700 (PDT) X-Received: by 2002:ac8:5c83:0:b0:517:63df:91a5 with SMTP id d75a77b69052e-52d2380c1b0mr7886581cf.19.1786126635760; Fri, 07 Aug 2026 11:17:15 -0700 (PDT) Received: from localhost (ip-86-49-241-13.bb.vodafone.cz. [86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080a743ffsm82614366b.23.2026.08.07.11.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:14 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 00/19] iommu/riscv: Enable MSI remapping, IOMMU_DMA and VFIO Date: Fri, 7 Aug 2026 20:16:54 +0200 Message-ID: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=Fp01OWrq c=1 sm=1 tr=0 ts=6a76212d cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=c92rfblmAAAA:8 a=uKVmUR9HeUr0h8foQc0A:9 a=kacYvNCVWA4VmyqE58fU:22 a=GvGzcOZaWPEFPQC_NcjD:22 X-Proofpoint-GUID: Lu7l8bSN8GQWG8j2jbQxQu6WBcxl42v8 X-Proofpoint-ORIG-GUID: Lu7l8bSN8GQWG8j2jbQxQu6WBcxl42v8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX8arI6o66u8lj fhnd3UJTrJOKq9RLDksSJedtKcRRPAhOdUhbHUdSWXUpetlqYbyR3cbN6oeFNPuvLzq3ZT7ostZ TmccNVBivvtiiKwLTd/Znco9PPUTDGZ+KWQt+3un1iPbbBJXPPATGmdCmeY8+qZ1tc9dRcQcKwq GQuRsWMkaBV6ThS3r7hBeI8fuWkCyFCDl3axIUmtl84ZJKdCV19AXSTvDzQmo1p+XkIGVKaGIzj nQgTUUy7xxFJP0w798bzasc5SkcJjqq9gsXc8sortnE/wj0ariBX+A8m5nC3CzPVyLgEmDJCd00 ulN4YgQpku7Z2FpsbbxZ0inaaVhuCyX9aN3U5uwyIbrj3Bu6tHFg974Omb1SxpOjZbgk8G9j7y1 soeG/IlJo2eRsCYf2RpKBPzlfNHiYP/zMGVE4hg+Nakbvzr5Ke/oL3Pk8hmK4DVtz/Woxdz3jke sbpDSFIYA0wwqgfunqA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX0IDdUJXGwAdQ V5rwN9FqzefSgPYBqhfBebv38QYb8qEPHx44uvTqOfAB0ujCTSRq3pOKPwwqXdHdpnuSdMsmpbH zbOUGuTH5eqrQoilmysseA35ECpRhK8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 clxscore=1015 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 This series adds MSI remapping for IMSIC so a device's MSI target gets translated the same way its DMA does, allowing RISC-V to enable IOMMU_DMA and paging domains by default. v1[1] used get_resv_regions() with IOMMU_RESV_DIRECT_RELAXABLE to identity map IMSIC pages, but that was rejected as only a workaround, and the proposal for v2 was to follow ARM's approach. ARM calls iommu_dma_prepare_msi() once at IRQ-alloc time, caches the IOVA on the msi_desc, and lets compose replay it via msi_msg_set_addr(). This series follows that structure by introducing an IRQ domain and a new iommu_dma_map_msi(). Like iommu_dma_prepare_msi(), it dispatches on the same domain cookie types. Unlike iommu_dma_prepare_msi(), it returns the IOVA to the caller instead of caching it on a descriptor. That allows the caller to collect all IOVAs needed (since IMSIC needs one IOVA per host IMSIC page). Like ARM, msi_msg_set_addr() is used at compose time to direct MSIs to the appropriate IOVAs. The divergence from ARM is required due to where the target address actually lives. ARM's doorbell PA is fixed per ITS instance (affinity changes only retarget hardware routing, never the composed address) so one IOVA cached at alloc time stays valid for the descriptor's lifetime. IMSIC doesn't have a fixed target, the MSI address itself changes on irq_set_affinity(), and that runs in atomic context, so mapping a fresh IOVA isn't an option. This series pre-maps every IMSIC page into a domain-wide PA-to-IOVA table at first IRQ-alloc time, and compose does an O(1) lookup to pick the right one. With the DMA path in place, v3 also carries the remaining plumbing needed for RISC-V PCIe device assignment through VFIO/KVM: the RISC-V IOMMU reports DMA cache-coherency capability, VFIO type1 and KVM_VFIO are enabled for RISC-V, defconfig enables IOMMUFD/VFIO as modules with cdev support, and the generic VFIO/iommufd selftests can be built for RISC-V. The interrupt-remapping domain does not yet validate MSI data, so VFIO still requires allow_unsafe_interrupts=1. Direct MSI routing to guest interrupt files (irqbypass) is not yet supported by this series. irqbypass will be posted separately on top. LLM-based coding assistants were used during development for code exploration ("super grep" as one of my colleagues calls it), patch review, test execution, and commit-message iteration, but all resulting code and commit messages were selected, reviewed, and finalized by me. Per-patch Assisted-by tags are omitted in light of the ongoing discussion about simplifying coding-assistant attribution[2]. Thanks, drew [1] https://lore.kernel.org/all/20260508212339.381933-1-andrew.jones@oss.qualcomm.com/ [2] https://lore.kernel.org/all/20260701-work-coding-assistants-v1-1-a20a94d1d606@kernel.org/ v3: - Addressed Sashiko's v2 comments[3] - Added RISC-V VFIO/KVM enablement patches and VFIO selftest build support - Capped SW MSI bitmap growth at 16K entries to simplify the growth arithmetic - Tracked live MSI allocations so domain replacement can rebuild MSI IOVA tables when no iommufd table can be copied - Add a patch to guard against identity <-> paging domain changes with in-flight MSIs [3] https://sashiko.dev/#/patchset/20260724151218.965929-1-andrew.jones@oss.qualcomm.com Andrew Jones (15): iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap iommufd: Add iommufd_sw_map_msi() iommu/dma: Add iommu_dma_sw_map_msi() iommu/dma: Add iommu_dma_map_msi() genirq/msi: Provide DOMAIN_BUS_MSI_REMAP irqchip/riscv-imsic: Compose MSI updates through the hierarchy iommu/riscv: Add IRQ domain for interrupt remapping iommu/riscv: Prepare info->domain for concurrent RCU read access iommu/riscv: Publish IOMMU_RESV_SW_MSI region for iommufd MSI remapping iommu/riscv: Pre-map IMSIC MSI targets iommu/riscv: Copy MSI IOVA table when replacing an iommufd domain iommu/riscv: Gate identity boundary switches with live MSIs iommu/riscv: Implement irq_compose_msi_msg for IMSIC remapping riscv: defconfig: Enable IOMMUFD and VFIO selftests/vfio: Allow building on RISC-V Tomasz Jeznach (4): iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V iommu/riscv: report iommu capabilities vfio: enable IOMMU_TYPE1 for RISC-V RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch arch/riscv/configs/defconfig | 4 + arch/riscv/kvm/Kconfig | 1 + drivers/iommu/Kconfig | 2 +- drivers/iommu/dma-iommu.c | 32 +- drivers/iommu/dma-iommu.h | 12 +- drivers/iommu/iommu-priv.h | 11 +- drivers/iommu/iommu.c | 104 +++++- drivers/iommu/iommufd/device.c | 3 +- drivers/iommu/iommufd/driver.c | 79 +++-- drivers/iommu/iommufd/hw_pagetable.c | 1 + drivers/iommu/iommufd/iommufd_private.h | 41 ++- drivers/iommu/riscv/Kconfig | 1 + drivers/iommu/riscv/Makefile | 2 +- drivers/iommu/riscv/iommu-ir.c | 353 +++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 100 ++++-- drivers/iommu/riscv/iommu.h | 41 +++ drivers/irqchip/irq-msi-lib.c | 8 +- drivers/irqchip/irq-riscv-imsic-platform.c | 27 +- drivers/vfio/Kconfig | 2 +- include/linux/iommu.h | 31 ++ include/linux/irqchip/riscv-imsic.h | 7 + include/linux/irqdomain_defs.h | 1 + tools/testing/selftests/vfio/Makefile | 2 +- 23 files changed, 749 insertions(+), 116 deletions(-) create mode 100644 drivers/iommu/riscv/iommu-ir.c -- 2.43.0