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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a1e7d48dcasm833503a12.15.2026.08.07.11.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:39 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 12/19] iommu/riscv: Gate identity boundary switches with live MSIs Date: Fri, 7 Aug 2026 20:17:06 +0200 Message-ID: <20260807181713.228535-13-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: O4jklWMHPqehre1n32ts1tJaw1eLilJh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX4syBCAG9tv79 hAdQDl9xYpF0S7DVa+yB6JyJ8wee3EtZo23aQyUJP6bb+J/bBOPd+9QTl3J4zpGRBoVSb8Fcd6A hVGfMynuXmS5c1ujSw06PUEF94IwBYBlgLupe8gokfbc1Tpqv91W0e+6mO/+5T7/+9MHDJ6m10L NLoSNmn6wV14podjz8KdYhROO4dBKjd52nusRtWgNJHEITR3NBNjALlXOJPbBzk9006EIYczI/p 9aAFf2Ayz6CJp0BXwWbq3S4C90LC/x0mzmiWjuBPXaaZ5pjRS9JHTMCtNNoQpQ4NO968Kv0nygO JABEkPwQ8c4Tv//2ECd9ggqdaZPGWB+pQIXgQ4aHWrjh7K9PVvueQfVlJSLzHpGHOczbBm42xRF HGOMbrZL2YZi4+1qxh0wXgSzvJZxIjDcTewHCU+e/RMDZNbc9Wju73VOTSzO7yhICzemEa72tEr kfaKSK5HoGKUL0AzN4A== X-Authority-Analysis: v=2.4 cv=bcBbluPB c=1 sm=1 tr=0 ts=6a762145 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=RNHjlBfCUNiOovmqR6wA:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: O4jklWMHPqehre1n32ts1tJaw1eLilJh X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXwD81oIbHf2W8 oBZp2GNvSS5sJ8sT8aCcL6Fc0V6DBdhqWVVAITOwMOWYE8HHxUGgScJr7lYMLORuYtzSMIRy4q5 hu+bjV8ZScvnk6C0eWAs2xFg6spuGJg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Reject identity-boundary domain transitions while a device still has allocated MSIs. The RISC-V IOMMU MSI compose path can run concurrently with domain attach and derives the MSI address rewrite policy from info->domain. Across an identity boundary, a stale decision can turn into a wrong addressing mode (IOVA vs PA), so require nr_msis == 0 when crossing between paging and identity domains. This is just a defensive guard since MSI state should be quiesced before crossing the identity boundary anyway. Do not gate paging <-> blocking: blocking is the fail-stop mode and must become available immediately, even with live MSIs. Do not gate paging -> paging: that path already uses nr_msis to ensure new-domain MSI table readiness before install. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 07287c0e72e7..f40db2cda417 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1272,10 +1272,14 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, struct riscv_iommu_domain *domain = iommu_domain_to_riscv(iommu_domain); struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_info *info = dev_iommu_priv_get(dev); + bool old_identity = old && old->type == IOMMU_DOMAIN_IDENTITY; struct pt_iommu_riscv_64_hw_info pt_info; u64 fsc, ta; int ret; + if (old_identity && info->nr_msis) + return -EBUSY; + pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) @@ -1394,6 +1398,10 @@ static int riscv_iommu_attach_identity_domain(struct iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_info *info = dev_iommu_priv_get(dev); + bool old_paging = old && (old->type & __IOMMU_DOMAIN_PAGING); + + if (old_paging && info->nr_msis) + return -EBUSY; riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, RISCV_IOMMU_PC_TA_V); riscv_iommu_bond_unlink(rcu_access_pointer(info->domain), dev); -- 2.43.0