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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a1e7d7648dsm828651a12.30.2026.08.07.11.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:42 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 13/19] iommu/riscv: Implement irq_compose_msi_msg for IMSIC remapping Date: Fri, 7 Aug 2026 20:17:07 +0200 Message-ID: <20260807181713.228535-14-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=Cb44Irrl c=1 sm=1 tr=0 ts=6a762149 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=wDfzXBFmrApTGnkBQMcA:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: 91knT7v5GCTtTrC67_F4QdaRZXrCIQy4 X-Proofpoint-ORIG-GUID: 91knT7v5GCTtTrC67_F4QdaRZXrCIQy4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX43/boWz66Cfy 34czKMwQzMxRCTx5GxWzjxZB3uEgvFOkmD1hM6Wr58/IqzcIy6rQvoxhfNMStqYezhXCN2R9PmF nnqh8hQaWhM50NGzdbracD/Q4Uaii747w/kDcbljNqDPaTqq+EWk5J52e8yV71MgX4Okrjd2/Xp fJEmWkO7pzI/D+86WSoet4H8LvUU8bo8zjcSWvgrbL73oF+jnV/JOrmgtN2PksWLEuARGu0vki5 mfVubTm1XB3+ZUM7zNxx9EtVdvU9h7kaoJpPXpzMi1A40tKiFU5LhrXZP5a+CbPbk6SQgtEA5y4 431AwD8388hOjzPHcErxnSOF5XuIrCX+D8AwKsjhmbf2VQpQ1ckDWaD6v6PGPpGK8OLXQBB2cd0 tNwHG+wqiQBE5lVckmyHNu0SnsLvpdctmW9dJHzm1ClnupNQYvfdZCmsp9B7Y/lY/mjWGS03PVu MDvpiU4ZYZV8AClItmA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX4eB4i68is7qZ +qxdNqM7M6n2myCXINVhxC9GXlLEjaM4w61s2cP9/Wee2XhAH/Qdf8NkZfEga+cmLjiJvpE4Bht vShUSYrgA+QwFTtqVHMQwkAfW0IA2uo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 Wire up irq_compose_msi_msg() on the IOMMU-IR irq chip to look up the pre-mapped IOVA for the target IMSIC page and rewrite the composed message to use it, redirecting MSI writes through the IOMMU instead of landing at the raw IMSIC physical address. The lookup is O(1), since the "extract" function used to build the table's index is also used here, which is necessary since the number of IMSICs may eventually be in the hundreds and irq_compose_msi_msg() may run in atomic context. domain->msi_iova is read here without domain->mutex, since compose can run in atomic context, and RCU only protects info->domain itself. Pair smp_store_release()/smp_load_acquire() on domain->msi_iova to ensure it's observably filled before publishing its pointer. That guarantees a non-NULL domain->msi_iova observed here is safe to use. A NULL domain->msi_iova falls back to the raw IMSIC physical address, same as when info->domain itself is NULL, since a live paging domain should not normally reach compose without a populated table. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 49 +++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 7d9a1eaca92e..98be3e3fddad 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -91,17 +91,56 @@ static int riscv_iommu_ir_build_msi_iova(struct riscv_iommu_domain *domain, stru return ret; } - domain->msi_iova = no_free_ptr(msi_iova); + /* Pair with smp_load_acquire() in riscv_iommu_ir_compose_msi_msg() */ + smp_store_release(&domain->msi_iova, no_free_ptr(msi_iova)); return 0; } +static void riscv_iommu_ir_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct riscv_iommu_info *info = data->domain->host_data; + struct riscv_iommu_domain *domain; + dma_addr_t *msi_iova; + struct msi_desc *desc; + phys_addr_t pa; + size_t idx; + + BUG_ON(irq_chip_compose_msi_msg(data->parent_data, msg)); + + desc = irq_data_get_msi_desc(data); + if (WARN_ON_ONCE(!desc)) + return; + + guard(rcu)(); + + domain = rcu_dereference(info->domain); + if (!domain) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + /* Pair with smp_store_release() in riscv_iommu_ir_build_msi_iova() */ + msi_iova = smp_load_acquire(&domain->msi_iova); + if (!msi_iova) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + pa = ((u64)msg->address_hi << 32) | msg->address_lo; + idx = riscv_iommu_ir_msi_iova_idx(pa); + + msi_desc_set_iommu_msi_iova(desc, msi_iova[idx], IMSIC_MMIO_PAGE_SHIFT); + msi_msg_set_addr(desc, msg, pa); +} + static struct irq_chip riscv_iommu_ir_irq_chip = { .name = "IOMMU-IR", .irq_ack = irq_chip_ack_parent, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_compose_msi_msg = riscv_iommu_ir_compose_msi_msg, }; static int riscv_iommu_ir_irq_domain_alloc_irqs(struct irq_domain *irqdomain, @@ -267,10 +306,12 @@ int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain, struc if (msi_iova) { guard(mutex)(&domain->mutex); - if (domain->msi_iova) + if (domain->msi_iova) { kfree(msi_iova); - else - domain->msi_iova = msi_iova; + } else { + /* Pair with smp_load_acquire() in riscv_iommu_ir_compose_msi_msg() */ + smp_store_release(&domain->msi_iova, msi_iova); + } return 0; } -- 2.43.0