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[86.49.241.13]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080cc386esm80002966b.45.2026.08.07.11.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 11:17:28 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v3 06/19] irqchip/riscv-imsic: Compose MSI updates through the hierarchy Date: Fri, 7 Aug 2026 20:17:00 +0200 Message-ID: <20260807181713.228535-7-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> References: <20260807181713.228535-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: D231vNtcCrahMj4CZMztS_yZO8a42njf X-Authority-Analysis: v=2.4 cv=SYbHsPRu c=1 sm=1 tr=0 ts=6a76213a cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=VPysOpcHbS0DNrM1Xqmyow==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=3qtCRIp3mPeaHrg9mH0A:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfX76wZwZHKbEMF YzvqkS6LNfw2I3n7aIsN9JP5Fu7Ff6UO1rQPbZSdDmbj6qSl9yBfpTsR8XRCVAFcMyacRQEUgoE LaVyIo8wgk/ylf94qzWZIeWlzV9JGK8= X-Proofpoint-GUID: D231vNtcCrahMj4CZMztS_yZO8a42njf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDE0MyBTYWx0ZWRfXzZ18p0pfh9ev FcMNo1nTBHNJO3JwGE/nOYpduF7BW7QlgesfYZOPA7XpgGU7UGHJ0N8FkqhtoWBu+9sp/5HUppa 2koaLkeF+ZT6pQlAIdnF9CGqitkE04JQ5Y49hLvDw9y19SuqfiPgiBUs0A6fDnxy63z9o4UMqux Q4TGkmyz63nYYoiwripgTPlJtV0oixdlCCgARciCXBoZYXbnSRGu9oftc3qvBsmYpL2KfjDezsK +gzUjQFJ3SMY4hhdIH+N6A2WPxoFfQYalC+PzZo1sO3Gi3e3//uL3a7FH09YnMKBWV4xA9dPeqL X/COPHPv/5JwlREB3KN3dYs/tJ1SWEuI1oPo32YrVOSIbvbsmQxFHSDqiW7pDctocwkqBpikVK/ xcs+xTT9hUsspvRoiqkH7KIZGdTWZTKwJP0JjrybRhoZK87x36vutOygbu+0BIsxqYVz6pd9/vC YCfGHhQ1pc7ruucFATw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070143 imsic_irq_set_affinity() wrote the new IMSIC target straight to the device via imsic_msi_update_msg(), bypassing the irqdomain hierarchy. That skips any intermediate IOMMU irqdomain sitting between IMSIC and the device, so a remapped device would keep the pre-remap physical address after every affinity change. Compose MSI updates via irq_chip_compose_msi_msg() starting from the top of the hierarchy instead, so an intermediate remap domain gets to translate the target before the device is written. For the temporary vector used by non-atomic affinity updates, compose the current vector through the hierarchy before d->chip_data is switched to the new vector, then replace only msg.data with the new local ID. This preserves the required old-address/new-data temporary target while also allowing an intermediate remap domain to refresh or clear any MSI IOVA state cached on the device's MSI descriptor. Moving the final write to after d->chip_data = new_vec is required because irq_chip_compose_msi_msg() reads d->chip_data. Keep it before updating effective affinity and migrating vector state so the device is retargeted before the old vector is disabled. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 27 ++++++++-------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 643c8e459611..5634641dc223 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -90,19 +90,12 @@ static void imsic_irq_compose_msg(struct irq_data *d, struct msi_msg *msg) } #ifdef CONFIG_SMP -static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *vec) -{ - struct msi_msg msg = { }; - - imsic_irq_compose_vector_msg(vec, &msg); - irq_data_get_irq_chip(d)->irq_write_msi_msg(d, &msg); -} - static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { + struct irq_data *top = irq_get_irq_data(d->irq); struct imsic_vector *old_vec, *new_vec; - struct imsic_vector tmp_vec; + struct msi_msg msg = { }; /* * Requirements for the downstream irqdomains (or devices): @@ -153,20 +146,20 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask */ if (!irq_can_move_in_process_context(d) && new_vec->local_id != old_vec->local_id) { - /* Setup temporary vector */ - tmp_vec.cpu = old_vec->cpu; - tmp_vec.local_id = new_vec->local_id; - /* Point device to the temporary vector */ - imsic_msi_update_msg(irq_get_irq_data(d->irq), &tmp_vec); + BUG_ON(irq_chip_compose_msi_msg(top, &msg)); + msg.data = new_vec->local_id; + irq_data_get_irq_chip(top)->irq_write_msi_msg(top, &msg); } - /* Point device to the new vector */ - imsic_msi_update_msg(irq_get_irq_data(d->irq), new_vec); - /* Update irq descriptors with the new vector */ d->chip_data = new_vec; + /* Point device to the new vector */ + memset(&msg, 0, sizeof(msg)); + BUG_ON(irq_chip_compose_msi_msg(top, &msg)); + irq_data_get_irq_chip(top)->irq_write_msi_msg(top, &msg); + /* Update effective affinity */ irq_data_update_effective_affinity(d, cpumask_of(new_vec->cpu)); -- 2.43.0