From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B7175390CB0; Sun, 9 Aug 2026 06:26:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786256776; cv=none; b=fWAN2qSmDFSfnXLsieMbnjCW57TciefzrCCU/Rx9DRHVAGoJ3pZRTNzc+n3fPle7Sf5fwm57BmKwR7KRXBw923niiHGDyO0dCy8HalPiir7eDY5JAda/1NP+4RA2X/Kf/QhwvTOXyaJfzBH3YZLkFwHdegGWDwkybcUp0U+ND+c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786256776; c=relaxed/simple; bh=wJaPGWOcZM9pRFM3yO8dRWF4o0ZcWmiCM1/HhdwQRDs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TXZJj5BiY8O6/WVyjjyp7pT0uJA6TOiZot7mZBBBZHX3OfLYjieNZinNVKiDq0wjoE8Aut+NSefsHsrKbDzQ0XilA4PudadY0OQxBfPkv1G5sr4ciJ9gQYmamgJj7boAGZ0dgwitEFwhlkOTpnKGk3BqkcpM1BfRGWhiqAabnIM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=hKTIclIk; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="hKTIclIk" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5BFB81570; Sat, 8 Aug 2026 23:26:10 -0700 (PDT) Received: from e127648.arm.com (unknown [10.57.4.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4C7D33F9A2; Sat, 8 Aug 2026 23:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1786256774; bh=wJaPGWOcZM9pRFM3yO8dRWF4o0ZcWmiCM1/HhdwQRDs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hKTIclIkqS40f+PN6n6BDrj97syFDaJVVZ1yuDARzX6vfllbyiK4ZSJSp9wygcUUG agZyZcCYhaS4oYaHrSZzvq4KkrUAdP5xTx4dkvi2TwcMRKzilmEYCBBaUEMgyM/wD8 0YqTte4BODUQpzQMfMO/khDA30oU10Uymv0GFMAU= From: Christian Loehle To: "Rafael J . Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Len Brown , Jie Zhan , Lifeng Zheng , Pierre Gondois , Sumit Gupta , Sudeep Holla , Ionela Voinescu , zhongqiu.han@oss.qualcomm.com, Christian Loehle , Sashiko Subject: [PATCH v3 04/15] ACPI: CPPC: Use 64-bit masks for register fields Date: Sun, 9 Aug 2026 07:25:38 +0100 Message-Id: <20260809062549.1415955-5-christian.loehle@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260809062549.1415955-1-christian.loehle@arm.com> References: <20260809062549.1415955-1-christian.loehle@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit MASK_VAL_READ() and MASK_VAL_WRITE() operate on u64 values but construct their masks with GENMASK(), whose type is unsigned long. On 32-bit kernels a field wider than 32 bits therefore produces an invalid shift or loses its upper bits. The Generic Address Structure permits QWord access units and the CPPC accessors implement 64-bit MMIO reads and writes. Use GENMASK_ULL() in both directions so the mask matches the value and supported access width on every architecture. Fixes: 60949b7b8054 ("ACPI: CPPC: Fix MASK_VAL() usage") Reported-by: Sashiko Link: https://sashiko.dev/#/patchset/20260724134251.1632824-1-christian.loehle%40arm.com Signed-off-by: Christian Loehle --- drivers/acpi/cppc_acpi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index e511cf8987a1..8da853e42de0 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -235,10 +235,10 @@ show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); /* Shift and apply the mask for CPC reads/writes */ #define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) & \ - GENMASK(((reg)->bit_width) - 1, 0)) + GENMASK_ULL(((reg)->bit_width) - 1, 0)) #define MASK_VAL_WRITE(reg, prev_val, val) \ - ((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \ - ((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \ + ((((val) & GENMASK_ULL(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \ + ((prev_val) & ~(GENMASK_ULL(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \ static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg) { -- 2.34.1