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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d16c50cfc1sm36768825ad.82.2026.08.10.06.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 06:18:32 -0700 (PDT) From: Qiang Yu Date: Mon, 10 Aug 2026 06:18:29 -0700 Subject: [PATCH] PCI: qcom: Block accesses to downstream devices on link down Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260810-ecam_blocker-v1-1-e588e07f68d4@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAKTPeWoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDC0MD3dTkxNz4pJz85OzUIt00CwPDJONEA6Ok5BQloJaCotS0zAqwcdG xEH5xaVJWanIJyAyl2loAMD7OvnAAAAA= X-Change-ID: 20260810-ecam_blocker-f801b3a02bcd To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786367912; l=4751; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=rqLb0leokYtiOyN/1dnd6EJFd31J2CbTZT4kf3PL2IQ=; b=YhPsVS5OFa870b2bUwMagYVlp0GHhXIZiqrQI2Cu/wj68P9gsbnXDBpkzBKcaOWZgw7/Keh+N wvZqF504kUMCOI07yRDlWJxwtvVJpR8oD0IveuK8HHw7q+BggqbUl3Y X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDExNCBTYWx0ZWRfX7/BvvOjH+iGk RiJm1uWN/5XLt9VyBQmkekbSxfsHnyO1sbb4Kq5+wDobkjiXeePieWkW/9yjvy8h+JVxK8TTNB5 Fi4ESIHZX7TGTAT3+hhOxGtWkL+G2h8= X-Authority-Analysis: v=2.4 cv=J6qaKgnS c=1 sm=1 tr=0 ts=6a79cfaa cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=GUKgOjlLqbvdKOx-lw4A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: XEjBkMs1WMthZ-CyhNMJ4WLEh5ulvCNU X-Proofpoint-ORIG-GUID: XEjBkMs1WMthZ-CyhNMJ4WLEh5ulvCNU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDExNCBTYWx0ZWRfX9yvbN/SPzTdA qgGNBcIwuSxndFZeowqvkKFeETirn7JSDOp7k2xrPF4WX0YZmd7bUleBgXR/6wjigN3SNWrXoY8 h0usLkk4OaUh9UNybNJ798qMsc18c8utleD5UyaFpDBQLh1hgqiNvgNlEPblcLKRY4uzmEcJ18m l/8q41DrF1CTswx7HpdyQys/4VEGnZB3Szr5A31/jqi1ApTyCbTQ2YChxq9ZsZPoztTm91dBHbF n3bgxOPI1rc0LmNcVfGPg3Z1na+tY4kqqr8bDuyKBfIrh7KTz1jOFHR/Rw8UVUWoUZDMSr4tN3a wMm63cM2C46DoWhIs9SppB/DAyzYU9GNtINi8FovNsQux6kfD2cA2qbz4PiN1Bag3VL/6IVJXIy L2MUmzQ1WSHtRRW1zNgoXpq/WpeXQqiHmYEHHfx6bOxOcttnCq7aExzD9GZc8tS5bVnlM7EufFL O9nTIjgePkFYeoLgtsw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_03,2026-08-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100114 After a PCIe link goes down, software may still access the BAR (MMIO) space or configuration space of devices behind that link before recovery has run. As the link is down, these accesses never complete, resulting in a storm of Completion Timeout AERs. Use the controller's ECAM blocker to drop these accesses to the PCIe address space as soon as the link-down interrupt fires, so that Completion Timeout AERs are reduced. The blocked range covers the entire address space (base 0x0, all-ones limit), since the Root Port's own DBI/iATU register space remains accessible regardless. The range is programmed once in the host init path, since the range registers are wiped by BCR reset. This leaves only the ECAM_BLOCKER_EN bit to be flipped from the link-down IRQ handler, so the blocker can be armed with a single fast register write for immediate effect. The subsequent Root Port reset re-initialises the controller, which clears the enable bit and re-programs the range for the fresh link. Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom.c | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index b58a607b713f..7005d989f6ff 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -73,6 +73,23 @@ #define PARF_BDF_TO_SID_TABLE_N 0x2000 #define PARF_BDF_TO_SID_CFG 0x2c00 +/* + * ECAM blocker range registers. The blocked range has a write pair + * (WR_BASE/WR_LIMIT) and a read pair (RD_BASE/RD_LIMIT); each address is + * split into a low (32-bit) and a HI (upper 32-bit) register. + */ +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c + +#define PARF_ECAM_BASE 0x380 +#define PARF_ECAM_BASE_HI 0x384 + /* ELBI registers */ #define ELBI_SYS_CTRL 0x04 #define ELBI_SYS_STTS 0x08 @@ -90,6 +107,7 @@ /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define ECAM_BLOCKER_EN BIT(26) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -1382,6 +1400,37 @@ static void qcom_pcie_configure_ports(struct qcom_pcie *pcie) dw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on); } +static void qcom_pcie_init_ecam_blocker(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + + /* ECAM base must match the DBI base address */ + writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); + writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); + + writel(0, pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); + writel(0, pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); + writel(U32_MAX, pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); + writel(U32_MAX, pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); + + writel(0, pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); + writel(0, pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); + writel(U32_MAX, pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); + writel(U32_MAX, pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); +} + +static void qcom_pcie_enable_ecam_blocker(struct qcom_pcie *pcie) +{ + u32 sys_ctrl; + + sys_ctrl = readl(pcie->parf + PARF_SYS_CTRL); + sys_ctrl |= ECAM_BLOCKER_EN; + writel(sys_ctrl, pcie->parf + PARF_SYS_CTRL); + + /* Flush the write so the blocker is enabled before this function returns */ + readl(pcie->parf + PARF_SYS_CTRL); +} + static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1422,6 +1471,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) qcom_pcie_configure_ports(pcie); + qcom_pcie_init_ecam_blocker(pcie); + qcom_pcie_perst_deassert(pcie); if (pcie->cfg->ops->config_sid) { @@ -1878,6 +1929,9 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) if (test_and_clear_bit(INT_ALL_LINK_DOWN, &status)) { dev_dbg(dev, "Received Link down event\n"); + + qcom_pcie_enable_ecam_blocker(pcie); + for_each_pci_bridge(port, pp->bridge->bus) { if (pci_pcie_type(port) == PCI_EXP_TYPE_ROOT_PORT) pci_host_handle_link_down(port); --- base-commit: 3de6add8d15430cde96c615fd156216676762bf9 change-id: 20260810-ecam_blocker-f801b3a02bcd Best regards, -- Qiang Yu