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Tue, 11 Aug 2026 01:40:19 -0700 (PDT) From: Mehmet Fide To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , Sasha Levin , Larisa Grigore , James Clark , Mark Brown , Vladimir Oltean , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6.12.y] spi: spi-fsl-dspi: Avoid setup_accel logic for DMA transfers Date: Tue, 11 Aug 2026 10:40:18 +0200 Message-ID: <20260811084018.3566861-1-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260810141437.2805389-1-mehmet.fide@gmail.com> References: <20260810141437.2805389-1-mehmet.fide@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some measurements on the hardware, in case they help decide this one. I ran the transfers that fail on 6.12 against 6.18.44, which carries cac7e5054115, on the same board (Colibri VF50, vf610, DSPI in DMA mode) with MOSI and MISO shorted at the connector, using spidev_test: 3, 5, 7, 9, 11 and 13 byte transfers: every byte comes back, in order. Even lengths and a single byte: fine as well. SPI_LSB_FIRST at 2, 3, 5, 8 and 13 bytes: bytes come back unchanged. Without the commit, the same odd length transfers lose the tail of the buffer, because the accel path packs into 16 bit frames and computes the word count as len / 2, and SPI_LSB_FIRST comes back byte swapped, because the accel helpers byte swap through cpu_to_be16() on top of the hardware LSBFE bit. That is what we have been carrying a local equivalent for. So the commit is what makes those transfers correct on this hardware, not just a saving of pointless repacking. Thanks, Mehmet