From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E91AD44684E for ; Tue, 11 Aug 2026 14:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786456904; cv=none; b=PhLZw2Iz8sd8R7bIdKJOMnqrIr1I7roGLKvp30oLh4FzPqfUV8h+sm4LRChEema0V7J9RI2LlTFDWK/DMrP2VRHSodaAiXNMSztvevk9HEM2uCgz1EBo8eWilja2YBSPcSiOokeErrJixQ1jQiHHF7Y8RDu6NsDa5ROLrGzanaE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786456904; c=relaxed/simple; bh=9mcbvLPAb5mlQfB6wIpqyZfFDQYLKrW6vxszOIeyRIM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ak+zMaWi8hBGQtxzBP2TBKlrTV5NLxsCRudqfopN7gBtxXUfkKJSsXBp/pZ9/5k+rUF+QMILkjDv1do3tFblo09YW+SBW/RCiAEy6VlgVFxk8MvBjRm+AoDv0cZK2QECGlDuHPCaR7JY/MBS0PrfogvVTBM6gQNqqeOrmIti7u8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dnVQBEwS; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dnVQBEwS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73DBC1F00A3A; Tue, 11 Aug 2026 14:01:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786456902; bh=5ERaMPsjwHcuWRT7KK06+ij6/U9aQH1xxiJrGBBvL1s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dnVQBEwSU7ZSnl+Gz3XvYWXW5SbVRLAUDeykXKtv44rNTMDSTQcBpndecLT63MIJV ETtcIGZzDcfAstoCc1M26RCjsuPFYzBC0xqU4pV0BL4u4P87i+YkIrLyDVHzimqAOi 5R9ETWWMCR56SPA33S2K0AfuNZHzRQLj2ExAaWAAnXVdiEMwjVDFiMROdgGX2jf3bP +hqZKIh4AJBrt6ugDJ6KqP6G67uhwtdzTM2hkvlG/1Nhxmc/fUbmgrLDQgptC6X2II iFclhEQASMDmf7ip4Kj31TGG1q1Sa5NdLGJah3FplAU3m8Pc7QfgchSzg7mvbxusod M1fI+VcliCFbw== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH 01/12] selftests/arm64: Remove big-endian support Date: Tue, 11 Aug 2026 15:01:20 +0100 Message-ID: <20260811140132.22778-2-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260811140132.22778-1-will@kernel.org> References: <20260811140132.22778-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Big-endian support on arm64 depends on BROKEN, so the arm64 selftests do not need to worry about testing this configuration any more. Remove the 128-bit byte-swapping helper from the fp-ptrace test and the big-endian definition of RSEQ_SIG_DATA from the rseq test. Signed-off-by: Will Deacon --- tools/testing/selftests/arm64/fp/fp-ptrace.c | 19 +------------------ tools/testing/selftests/rseq/rseq-arm64.h | 5 ----- 2 files changed, 1 insertion(+), 23 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/selftests/arm64/fp/fp-ptrace.c index 22c584b78be5..77d630444996 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -112,23 +112,6 @@ static void handle_alarm(int sig, siginfo_t *info, void *context) got_alarm = true; } -#ifdef CONFIG_CPU_BIG_ENDIAN -static __uint128_t arm64_cpu_to_le128(__uint128_t x) -{ - u64 a = swab64(x); - u64 b = swab64(x >> 64); - - return ((__uint128_t)a << 64) | b; -} -#else -static __uint128_t arm64_cpu_to_le128(__uint128_t x) -{ - return x; -} -#endif - -#define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) - static bool sve_supported(void) { return getauxval(AT_HWCAP) & HWCAP_SVE; @@ -897,7 +880,7 @@ static void fpsimd_to_sve(__uint128_t *v, char *z, int vl) for (i = 0; i < __SVE_NUM_ZREGS; i++) { p = (__uint128_t *)&z[__SVE_ZREG_OFFSET(vq, i)]; - *p = arm64_cpu_to_le128(v[i]); + *p = v[i]; } } diff --git a/tools/testing/selftests/rseq/rseq-arm64.h b/tools/testing/selftests/rseq/rseq-arm64.h index 21e1626a7235..f9fecf941bf2 100644 --- a/tools/testing/selftests/rseq/rseq-arm64.h +++ b/tools/testing/selftests/rseq/rseq-arm64.h @@ -12,12 +12,7 @@ * matches code endianness. */ #define RSEQ_SIG_CODE 0xd428bc00 /* BRK #0x45E0. */ - -#ifdef __AARCH64EB__ -#define RSEQ_SIG_DATA 0x00bc28d4 /* BRK #0x45E0. */ -#else #define RSEQ_SIG_DATA RSEQ_SIG_CODE -#endif #define RSEQ_SIG RSEQ_SIG_DATA -- 2.55.0.679.g6767b8d81c-goog