From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0159F448CF4 for ; Tue, 11 Aug 2026 14:01:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786456910; cv=none; b=MnNDIby50Yenq8/XCTap7GvOUd3feHqAIfPKwvaIETq6jn3Hh6CVnl9OKCPNt3XLvEPxUIpmeH8QBt59uj6ix7582gewBwThR69JN7WapTkgiw8m6flonpjHtGI3sS3nYOS4vnv9a709F3G/9DYmFzHPndPHQxRBlkJD8L4QEgE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786456910; c=relaxed/simple; bh=dXqFQwIfYkpiUQ7XemLsptn8czI+wzeDrc56PxdWZWM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jQZhkJLcc9s1UZYbNvsXyMK+t0CWZpeddN5ufe8szgn/lvB+vjsjFv3PZ2pQ4Qu1exHvMnVobcZnfGvu2aYHK+l38RwGTaG+FOsHs0tIonEXJ8iV06+MXZoe3YdyhJjMAFMEJVs3A+Dbo9xt3Wv3bkZsRmbmNfi4INcS+hmHXuw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DN2Y6ju9; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DN2Y6ju9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4E9F51F000E9; Tue, 11 Aug 2026 14:01:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786456908; bh=n9dRmmOuvF3CPO8z7383jINPuZ9NkflcJlXq8mm+S3Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=DN2Y6ju9Mjq5AHx1VMdhsh7UePFooV9VT0RkY20PoWnkbINa61BzJ0Ze7agRymuvF req8t+ejvPx66nM1ugGqXKm+4ddFcUyP3vrXBia9gHygJQEeeHsIvnl3VXOQmOTx8s fi9G07RphYIExpeQu+fRzKK+BabPhiq70AILJlNKMCWfSwT4YmkiP5JFHFEA1bsNVS B6exa9qMRyMdyAwM3Wr3MhGIjhp+ktw+8nZZ0evQqdOvb/fmHd9wpv9/0eqdxStOxo TLg+3qtrnlFgDqe3WmYoqB7V3co12161p0b0+gX63jB5gWlRspt6IoHLIMJFUrpzCH TkS2lDf7AbcGA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH 03/12] arm64: crypto: Assume a little-endian kernel Date: Tue, 11 Aug 2026 15:01:22 +0100 Message-ID: <20260811140132.22778-4-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260811140132.22778-1-will@kernel.org> References: <20260811140132.22778-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Commit 5276ea17a23c ("lib/crc: arm64: Assume a little-endian kernel") removed all usage of the CPU_LE()/CPU_BE() macros from the arm64 CRC assembly now that big-endian support depends on BROKEN. Do the same for the crypto assembly code. Signed-off-by: Will Deacon --- arch/arm64/crypto/aes-ce-ccm-core.S | 4 ++-- arch/arm64/crypto/aes-neonbs-core.S | 4 ++-- arch/arm64/crypto/ghash-ce-core.S | 6 +++--- arch/arm64/crypto/sm4-ce-cipher-core.S | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/crypto/aes-ce-ccm-core.S b/arch/arm64/crypto/aes-ce-ccm-core.S index f2624238fd95..c2e8f500da14 100644 --- a/arch/arm64/crypto/aes-ce-ccm-core.S +++ b/arch/arm64/crypto/aes-ce-ccm-core.S @@ -50,7 +50,7 @@ ld1 {v0.16b}, [x5] /* load mac */ cbz x2, ce_aes_ccm_final ldr x8, [x6, #8] /* load lower ctr */ -CPU_LE( rev x8, x8 ) /* keep swabbed ctr in reg */ + rev x8, x8 /* keep swabbed ctr in reg */ 0: /* outer loop */ ld1 {v1.8b}, [x6] /* load upper ctr */ prfm pldl1strm, [x1] @@ -73,7 +73,7 @@ CPU_LE( rev x8, x8 ) /* keep swabbed ctr in reg */ eor v0.16b, v0.16b, v2.16b /* xor mac with pt ^ rk[last] */ st1 {v6.16b}, [x0], #16 /* write output block */ bne 0b -CPU_LE( rev x8, x8 ) + rev x8, x8 str x8, [x6, #8] /* store lsb end of ctr (BE) */ cbnz x7, ce_aes_ccm_final st1 {v0.16b}, [x5] /* store mac */ diff --git a/arch/arm64/crypto/aes-neonbs-core.S b/arch/arm64/crypto/aes-neonbs-core.S index baf450717b24..ba1f981a5464 100644 --- a/arch/arm64/crypto/aes-neonbs-core.S +++ b/arch/arm64/crypto/aes-neonbs-core.S @@ -824,8 +824,8 @@ SYM_FUNC_START(aesbs_ctr_encrypt) frame_push 0 ldp x7, x8, [x5] ld1 {v0.16b}, [x5] -CPU_LE( rev x7, x7 ) -CPU_LE( rev x8, x8 ) + rev x7, x7 + rev x8, x8 adds x8, x8, #1 adc x7, x7, xzr diff --git a/arch/arm64/crypto/ghash-ce-core.S b/arch/arm64/crypto/ghash-ce-core.S index 33772d8fe6b5..ba350d57fc76 100644 --- a/arch/arm64/crypto/ghash-ce-core.S +++ b/arch/arm64/crypto/ghash-ce-core.S @@ -148,7 +148,7 @@ SYM_FUNC_START(pmull_ghash_update_p64) sub w0, w0, #1 3: /* multiply XL by SHASH in GF(2^128) */ -CPU_LE( rev64 T1.16b, T1.16b ) + rev64 T1.16b, T1.16b ext T2.16b, XL.16b, XL.16b, #8 ext IN1.16b, T1.16b, T1.16b, #8 @@ -272,7 +272,7 @@ SYM_FUNC_END(pmull_ghash_update_p64) cbz x0, 3f // tag only? ldr w8, [x5, #12] // load lower counter -CPU_LE( rev w8, w8 ) + rev w8, w8 0: mov w9, #4 // max blocks per round add x10, x0, #0xf @@ -380,7 +380,7 @@ CPU_LE( rev w8, w8 ) ret 5: -CPU_LE( rev w8, w8 ) + rev w8, w8 str w8, [x5, #12] // store lower counter st1 {XL.2d}, [x4] b 4b diff --git a/arch/arm64/crypto/sm4-ce-cipher-core.S b/arch/arm64/crypto/sm4-ce-cipher-core.S index 4ac6cfbc5797..1682d727e097 100644 --- a/arch/arm64/crypto/sm4-ce-cipher-core.S +++ b/arch/arm64/crypto/sm4-ce-cipher-core.S @@ -18,7 +18,7 @@ SYM_FUNC_START(sm4_ce_do_crypt) ld1 {v8.4s}, [x2] ld1 {v0.4s-v3.4s}, [x0], #64 -CPU_LE( rev32 v8.16b, v8.16b ) + rev32 v8.16b, v8.16b ld1 {v4.4s-v7.4s}, [x0] sm4e v8.4s, v0.4s sm4e v8.4s, v1.4s @@ -30,7 +30,7 @@ CPU_LE( rev32 v8.16b, v8.16b ) sm4e v8.4s, v7.4s rev64 v8.4s, v8.4s ext v8.16b, v8.16b, v8.16b, #8 -CPU_LE( rev32 v8.16b, v8.16b ) + rev32 v8.16b, v8.16b st1 {v8.4s}, [x1] ret SYM_FUNC_END(sm4_ce_do_crypt) -- 2.55.0.679.g6767b8d81c-goog