From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-188.mta0.migadu.com (out-188.mta0.migadu.com [91.218.175.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F21D137B02D for ; Tue, 11 Aug 2026 23:03:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.188 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489424; cv=none; b=J26ixCblClohZ/HVSXkdzuwMNvy3I5Kh/3jV9yTQ2jXQR1ndsV0o4/tqefwKIIhZeMhezdBj0HLCFum/j02s7QjIWu/XOF535L4bjJdgX0NH7ca7VI9LzE9ZLatR4y93vaTGF0STFvSon2bRSiY1WzDqEwM+SJ8NAzKmq6QLXl4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786489424; c=relaxed/simple; bh=+LKFcMApSCsnOhk6ssXJV4RsC8/mPP/K8TE2ue8ghXA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=AW1IeQGBZ0ECWStde7yYh4RFBPGNDLF8C/SN0n5kSwDe/91NL2oY+d4YyoSXJ1esry/DwcSXJsx82SXreSBR69mg02WCmBWR2ZnaNuqKHSelGounhU2DPoYoXW2moYeLHz+OLPZEiYzwKV25nE6hB09xE+U6ZWSRvSAPCjSBato= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=uhqDK676; arc=none smtp.client-ip=91.218.175.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="uhqDK676" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1786489409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=8UvpAj+F5vT5g4mqj62S8++wLHXXvTKlCPt/B/F/wRA=; b=uhqDK676wfkne/SJg/zrMRXEuKOCSYL5QtpyKgvrDo0pT2IcJKOScNB6Dmfx/xf3WPo8SH 6f18T8GkU74//HaIFjg30nYvgx2HUPxgBLLYF9sln+zlLRBujxWy4Toy7aYHmFxjMqCaQC z0RcgOXAHRHzBL7Qxh87wLjLX496R2I= From: Jinyu Tang To: Anup Patel , Anup Patel , Paolo Bonzini , Sean Christopherson Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra , Paul Walmsley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Conor Dooley , Yong-Xuan Wang , Nutty Liu , Jinyu Tang , Jinyu Tang Subject: [PATCH v2 0/3] KVM: riscv: Add KVM_PRE_FAULT_MEMORY support Date: Wed, 12 Aug 2026 07:03:13 +0800 Message-ID: <20260811230316.218770-1-jinyu.tang@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT This series adds RISC-V support for the generic KVM_PRE_FAULT_MEMORY vcpu ioctl and enables the existing generic KVM selftest for RISC-V. KVM_PRE_FAULT_MEMORY lets userspace ask KVM to populate stage-2 mappings for a GPA range before running a vCPU that is expected to access that range. x86 already supports the ioctl; RISC-V currently falls back to normal first-touch G-stage faults. Patch 1 implements the RISC-V arch hook using the existing G-stage map path. Patch 2 fixes the RISC-V selftest page-table walker for Sv57, which can be selected as the default guest mode. Patch 3 enables pre_fault_memory_test for RISC-V. Tested with pre_fault_memory_test on a RISC-V KVM host. Changes in v2: - Drop the per-test guest_modes_append_default() call from pre_fault_memory_test.c. RISC-V already initializes supported and default guest modes from kvm_selftest_arch_init(), which is called by the common kvm_selftest_init() constructor, as suggested by Sean. Jinyu Tang (3): KVM: riscv: Implement KVM_PRE_FAULT_MEMORY KVM: selftests: Add RISC-V Sv57 page table indexing KVM: selftests: Enable pre_fault_memory_test for RISC-V arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/gstage.c | 3 ++ arch/riscv/kvm/mmu.c | 33 +++++++++++++++++++ arch/riscv/kvm/vm.c | 1 + tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/include/riscv/processor.h | 6 ++++ .../selftests/kvm/lib/riscv/processor.c | 2 ++ 7 files changed, 47 insertions(+) -- 2.43.0