From: Leon Romanovsky <leon@kernel.org>
To: "Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Saket Dumbre <saket.dumbre@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Logan Gunthorpe <logang@deltatee.com>
Cc: linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
Lukas Wunner <lukas@wunner.de>,
"Natu, Mahesh" <mahesh.natu@intel.com>
Subject: [PATCH RFC 3/7] PCI/P2PDMA: Authorize HMAT-described cross-host-bridge P2P
Date: Wed, 12 Aug 2026 22:47:40 +0300 [thread overview]
Message-ID: <20260812-hmat-p2p-v1-3-75ac41380585@nvidia.com> (raw)
In-Reply-To: <20260812-hmat-p2p-v1-0-75ac41380585@nvidia.com>
From: Leon Romanovsky <leonro@nvidia.com>
PCI P2PDMA rejects cross-host-bridge transactions unless the platform
matches hard-coded CPU or host-bridge knowledge. That excludes capable
systems, requires recurring kernel whitelist updates, and cannot represent
firmware-qualified directional paths.
Accept a reachable ordered HMAT path from requester to completer as
platform authorization. Missing entries, unreachable entries, and UIO-only
entries do not authorize ordinary DMA. The existing safety boundary remains
in force when firmware does not describe a usable ordered path.
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
---
drivers/pci/p2pdma.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
index 34929bc6efb6..dd300d2e9887 100644
--- a/drivers/pci/p2pdma.c
+++ b/drivers/pci/p2pdma.c
@@ -9,6 +9,7 @@
*/
#define pr_fmt(fmt) "pci-p2pdma: " fmt
+#include <linux/acpi.h>
#include <linux/ctype.h>
#include <linux/dma-map-ops.h>
#include <linux/pci-p2pdma.h>
@@ -733,6 +734,57 @@ static bool host_bridge_whitelist(struct pci_dev *a, struct pci_dev *b,
return false;
}
+#ifdef CONFIG_ACPI
+static int pci_host_bridge_pxm(struct pci_dev *pdev)
+{
+ struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
+ struct acpi_device *adev;
+ const char *uid_str;
+ u32 uid;
+
+ adev = to_acpi_device_node(host->dev.fwnode);
+ if (!adev)
+ return -ENODEV;
+
+ uid_str = acpi_device_uid(adev);
+ if (!uid_str || kstrtou32(uid_str, 0, &uid))
+ return -ENODEV;
+
+ return acpi_get_genport_proximity_domain(uid);
+}
+#else
+static int pci_host_bridge_pxm(struct pci_dev *pdev)
+{
+ return -ENODEV;
+}
+#endif
+
+/*
+ * Check whether platform firmware describes, via an HMAT PCIe P2P Latency and
+ * Bandwidth Information Structure, a reachable ordered (non-UIO) P2P path from
+ * the client's host bridge to the provider's host bridge. When it does, the
+ * platform vouches for cross-host-bridge P2P even if the root complex is not
+ * in the static whitelist.
+ *
+ * The client is the requester of the P2P transactions and the provider is the
+ * completer, so the client's host bridge is the HMAT initiator and the
+ * provider's host bridge is the HMAT target. UIO-only paths are described by
+ * firmware but are not (yet) used to authorize ordered DMA.
+ */
+static bool host_bridge_hmat_p2p(struct pci_dev *provider, struct pci_dev *client)
+{
+ struct access_coordinate coord;
+ int init_pxm, targ_pxm;
+
+ init_pxm = pci_host_bridge_pxm(client);
+ targ_pxm = pci_host_bridge_pxm(provider);
+ if (init_pxm < 0 || targ_pxm < 0)
+ return false;
+
+ return acpi_get_p2p_coordinates(init_pxm, targ_pxm, HMAT_P2P_NON_UIO,
+ &coord) == 0;
+}
+
static unsigned long map_types_idx(struct pci_dev *client)
{
return (pci_domain_nr(client->bus) << 16) | pci_dev_id(client);
@@ -890,9 +942,10 @@ calc_map_type_and_dist(struct pci_dev *provider, struct pci_dev *client,
map_through_host_bridge:
if (!cpu_supports_p2pdma() &&
+ !host_bridge_hmat_p2p(provider, client) &&
!host_bridge_whitelist(provider, client, verbose)) {
if (verbose)
- pci_warn(client, "cannot be used for peer-to-peer DMA as the client and provider (%s) do not share an upstream bridge or whitelisted host bridge\n",
+ pci_warn(client, "cannot be used for peer-to-peer DMA as the client and provider (%s) do not share an upstream bridge, whitelisted host bridge, or HMAT-described P2P path\n",
pci_name(provider));
map_type = PCI_P2PDMA_MAP_NOT_SUPPORTED;
}
--
2.55.0
next prev parent reply other threads:[~2026-08-12 19:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 19:47 [PATCH RFC 0/7] PCI/HMAT: Describe P2PDMA reachability and performance Leon Romanovsky
2026-08-12 19:47 ` [PATCH RFC 1/7] ACPICA: Define PCIe P2P latency and bandwidth information Leon Romanovsky
2026-08-13 10:13 ` Rafael J. Wysocki (Intel)
2026-08-13 11:01 ` Leon Romanovsky
2026-08-12 19:47 ` [PATCH RFC 2/7] ACPI: HMAT: Make PCIe P2P paths available to consumers Leon Romanovsky
2026-08-12 19:47 ` Leon Romanovsky [this message]
2026-08-12 19:47 ` [PATCH RFC 4/7] PCI/P2PDMA: Prefer providers with better HMAT performance Leon Romanovsky
2026-08-14 3:50 ` Logan Gunthorpe
2026-08-16 12:38 ` Leon Romanovsky
2026-08-17 16:09 ` Logan Gunthorpe
2026-08-17 18:27 ` Leon Romanovsky
2026-08-12 19:47 ` [PATCH RFC 5/7] ACPI: HMAT: Add KUnit tests for PCIe P2P matrix semantics Leon Romanovsky
2026-08-12 19:47 ` [PATCH RFC 6/7] PCI/P2PDMA: Add KUnit tests for HMAT policy boundaries Leon Romanovsky
2026-08-12 19:47 ` [PATCH RFC 7/7] PCI/P2PDMA: Add KUnit tests for HMAT provider ranking Leon Romanovsky
2026-08-24 20:15 ` [PATCH RFC 0/7] PCI/HMAT: Describe P2PDMA reachability and performance Alison Schofield
2026-08-24 20:24 ` Natu, Mahesh
2026-08-26 14:08 ` Leon Romanovsky
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