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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141245a9f70sm9942865c88.15.2026.08.12.01.31.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Aug 2026 01:31:13 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 12 Aug 2026 14:00:56 +0530 Subject: [PATCH v2 2/2] i2c: qcom-geni: add I2C frequency table for 32 MHz firmware-based SEs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260812-ipq5424_i2c_scl_updates-v2-2-e09cd39d01d7@oss.qualcomm.com> References: <20260812-ipq5424_i2c_scl_updates-v2-0-e09cd39d01d7@oss.qualcomm.com> In-Reply-To: <20260812-ipq5424_i2c_scl_updates-v2-0-e09cd39d01d7@oss.qualcomm.com> To: Mukesh Kumar Savaliya , Viken Dadhaniya , Andi Shyti , Manikanta Mylavarapu , Bjorn Andersson , Konrad Dybcio Cc: Mukesh Kumar Savaliya , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Proofpoint-ORIG-GUID: o8BAM7CyLjdLbdJYJuyq5ia395spGVsO X-Authority-Analysis: v=2.4 cv=IO4yzAvG c=1 sm=1 tr=0 ts=6a7c2f53 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=ZgzYBJRxMK-01OSQGPUA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEyMDA2NyBTYWx0ZWRfX4TYucvyyoA6x Zm8YmOeXFo0ky4IYwCVOCS+lJjx39/Q4qtDfuU1UfAcAuDAQujMdVp7Ak227JW6QnobsiYcEzaV FE/pXUtrhiCU4v7ddyUIdEtdO9dRJ3KGKvY5HHE2R273MgJeWD+/yhF1pkOA9jiW0u5TBpMll9I 5i/NfJ9U/2v5VB+4MYAYh3HmZYch4xyrrIHRfHZIauQ3BSGfytNCKodiMsHeG4UpNg2Z7lQjcqb 07MrjR0JIEcFYbxvJRR+4lVmfnby2tbDMVaHtqphuetl7HwXgOfUY7k2C/KNaLMwCfKCx51RpgL jih7KH+1L/iu0hRGKZln0+4U/A67qo/dfVZlzrq7wksWsjveMx8APaVyVAoWCGn2l41PKNWlOG7 NkrUQIucFAX2C+14Slwn7v39kQNkzJAPM+BE/xqKCCZbrePxoIZHkMHrcyTIiJR1JjG1p+NsV0l ORxNJogbX9HD9w5uwLA== X-Proofpoint-GUID: o8BAM7CyLjdLbdJYJuyq5ia395spGVsO X-Proofpoint-Spam-Info: AW1haW4tMjYwODEyMDA2NyBTYWx0ZWRfXx7S+JeDqMz2+ CXer8H/pZEW/AXuuLsH3/CwNAodtQY5RVvGvi5Z93L4H0uL3Tw3IgZ/62LvRTxETeA6hIIHJ9d3 sA1NaFfXXvKBEGiRnsU9eTN390LhTrU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-12_02,2026-08-10_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608120067 On IPQ5424, the I2C controller can operate on both RTL-hardened SEs and firmware-based SEs. As documented in commit 506bb2ab0075 ("i2c: qcom-geni: Support systems with 32MHz serial engine clock"), in IPQ5424 SEs use a 32 MHz source clock. The existing frequency table does not provide the required SCL timing parameters for firmware-based SEs. Add a dedicated frequency table using the SCL counter values recommended by the hardware design team and select it for firmware-based SEs to achieve the target bus frequencies. Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the required clocks have been enabled. Signed-off-by: Kathiravan Thirumoorthy --- drivers/i2c/busses/i2c-qcom-geni.c | 25 ++++++++++++++++++------- include/linux/soc/qcom/geni-se.h | 1 + 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 00013b41a6f5..15835f10b062 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -187,19 +187,28 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { }; /* source_clock = 32 MHz */ -static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_minicore[] = { { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 }, { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, {} }; +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_fwcore[] = { + { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 }, + { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 }, + { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 }, + {} +}; + static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) { const struct geni_i2c_clk_fld *itr; + bool is_minicore = FIELD_GET(GEN_USE_MINICORES, + readl_relaxed(gi2c->se.base + SE_HW_PARAM_2)); if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) - itr = geni_i2c_clk_map_32mhz; + itr = is_minicore ? geni_i2c_clk_map_32mhz_minicore : geni_i2c_clk_map_32mhz_fwcore; else itr = geni_i2c_clk_map_19p2mhz; @@ -1046,6 +1055,13 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) return ret; } + ret = geni_i2c_clk_map_idx(gi2c); + if (ret) { + return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", + gi2c->clk_freq_out); + goto err; + } + proto = geni_se_read_proto(&gi2c->se); if (proto == GENI_SE_INVALID_PROTO) { ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); @@ -1109,11 +1125,6 @@ static int geni_i2c_resources_init(struct geni_se *se) if (ret) return ret; - ret = geni_i2c_clk_map_idx(gi2c); - if (ret) - return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", - gi2c->clk_freq_out); - return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, Bps_to_icc(gi2c->clk_freq_out)); } diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 29a53bbc0dd4..7e8c0bb6d674 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -331,6 +331,7 @@ struct geni_se { #define RX_FIFO_DEPTH_SHFT 16 /* SE_HW_PARAM_2 fields */ +#define GEN_USE_MINICORES BIT(12) #define PROG_RAM_DEPTH_MSK GENMASK(10, 0) #define HW_VER_MAJOR_MASK GENMASK(31, 28) -- 2.34.1