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(unknown [10.28.34.91]) by maili.marvell.com (Postfix) with ESMTP id 5F7253F7041; Wed, 12 Aug 2026 04:45:17 -0700 (PDT) From: Umesh Kumar To: Andy Shevchenko , Andi Shyti CC: Mika Westerberg , , , , Umesh Kumar Subject: [PATCH v3] i2c: designware: Enable SAR in slave mode for Multiple SAR controllers Date: Wed, 12 Aug 2026 17:15:14 +0530 Message-ID: <20260812114514.3817964-1-ukumar@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260804041842.3205356-1-ukumar@marvell.com> References: <20260804041842.3205356-1-ukumar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Authority-Analysis: v=2.4 cv=QJ1YgALL c=1 sm=1 tr=0 ts=6a7c5cd3 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=M5GUcnROAAAA:8 a=QyXUC8HyAAAA:8 a=9AgWGjU10VSWC3nbNTEA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: hENFzgLBJO9PfPlSIeBfCwSx9SPL-3t_ X-Proofpoint-ORIG-GUID: hENFzgLBJO9PfPlSIeBfCwSx9SPL-3t_ X-Proofpoint-Spam-Info: AW1haW4tMjYwODEyMDA5NSBTYWx0ZWRfX2WaI3EzY/mmY F6a1DL/L8X0iYQXVoav0PDmYdC1Iw4hqCOmnR0INCF5+I0uUi1ahsdE/10CA6dl5mCxy2NG9Sbj AblKOHUNPfw4TWurATt3YXSK8oD8vJU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEyMDA5NSBTYWx0ZWRfX9d4A8ryd6NOj LQgTDrMo5cjkhQbesbCMhEg+7rKAxN0LU9/J1EqXC8LaTwZ6iGp+4QOltn+zLcEQHjnMga0Tt9n gNTf0/AFCgQgukyeoo5ksgkmT5pvETWVD5dx791MWnoCpLqWKjx1LQdZh4szC5x2hW0Cwy4O6a6 vFYIdOvb0uDfYQiZ5dodYIeoqxpb3OeGuX3OVOBRfkbQswNK4Cm+rJuVvc/YLy8u9M+hJdT8wzu iakg6slm5EaqusUdfkF5fYqmsOz8wct9LV30n3+sbvYbICbNF3YS8ujF0CrVnNwIeK83aUWY/be Xr1RGs2IjpQX7Cm7TG3vFqzlmtIM0BOj6PKu9QmT+Zb4DkPtjIdt6iyKwlFOog9oPuMf26eZKYe A6cz/P90J0GqRRwmUEjeBe6fQFemJx4GIPmzZ1bqYocm123TOQ4g5mgdQC9BASg/BCJjBqCUIK9 OkHmEdmKzDRev8yoVnw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-12_03,2026-08-12_01,2025-10-01_01 DesignWare controllers synthesised with the Multiple SAR feature (e.g. Marvell CN20K) gate the primary slave address behind IC_ENABLE.SAR_EN (bit 19). Per the Synopsys DW_apb_i2c DataBook (Multiple SAR feature), when this bit is set the core acknowledges the address matching IC_SAR; otherwise the address is NACKed. The slave enable path writes only IC_ENABLE.ENABLE (bit 0), so on such controllers the target never ACKs its address and a remote master cannot reach it. Set SAR_EN together with ENABLE when entering slave mode. The bit is reserved (and ignored) on single-SAR controllers, so existing users are unaffected. Signed-off-by: Umesh Kumar Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-common.c | 10 +++++++++- drivers/i2c/busses/i2c-designware-core.h | 8 ++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c index 4dc57fd56170..8ed0b588d67b 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -374,7 +374,15 @@ static void i2c_dw_configure_mode(struct dw_i2c_dev *dev, int mode) regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); regmap_write(dev->map, DW_IC_SAR, dev->slave->addr); regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); - __i2c_dw_enable(dev); + /* + * Per the Synopsys DW_apb_i2c DataBook (Multiple SAR feature), + * controllers synthesised with multiple SARs only acknowledge + * traffic to IC_SAR when IC_ENABLE.SAR_EN is set; a plain enable + * is not enough. The bit is reserved (ignored) on single-SAR + * controllers. + */ + regmap_write(dev->map, DW_IC_ENABLE, + DW_IC_ENABLE_ENABLE | DW_IC_ENABLE_SAR_EN); break; default: WARN(1, "Invalid mode %d\n", mode); diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index 9d8d104cc391..b237d093c562 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -125,6 +125,14 @@ #define DW_IC_ENABLE_ENABLE BIT(0) #define DW_IC_ENABLE_ABORT BIT(1) +/* + * IC_ENABLE.SAR_EN, per the Synopsys DW_apb_i2c DataBook (Multiple SAR + * feature): on controllers synthesised with multiple SARs (e.g. Marvell + * CN20K) the primary slave address (IC_SAR) is only acknowledged when this + * bit is set. Must be programmed while IC_ENABLE.ENABLE is 0. Reserved on + * single-SAR controllers. + */ +#define DW_IC_ENABLE_SAR_EN BIT(19) #define DW_IC_STATUS_ACTIVITY BIT(0) #define DW_IC_STATUS_TFE BIT(2) -- 2.43.0