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Wed, 12 Aug 2026 09:45:21 -0700 (PDT) From: Archit Anant To: jic23@kernel.org Cc: dlechner@baylibre.com, andy@kernel.org, nuno.sa@analog.com, u.kleine-koenig@baylibre.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Anant Subject: [PATCH v3 7/8] iio: adc: ti-ads1015: replace custom shift macros with FIELD_PREP/GET Date: Wed, 12 Aug 2026 22:14:32 +0530 Message-Id: <20260812164433.23011-8-architanant5@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260812164433.23011-1-architanant5@gmail.com> References: <20260812164433.23011-1-architanant5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The driver currently uses custom _SHIFT macros and manual bitwise operations to read and write to the configuration register. Modernize the bitwise logic by replacing all manual shifts with the standard FIELD_PREP() and FIELD_GET() macros from . This improves readability and prevents potential bitwise errors. Remove the now-unused _SHIFT macros from the top of the file. Suggested-by: Jonathan Cameron Signed-off-by: Archit Anant --- drivers/iio/adc/ti-ads1015.c | 39 ++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/iio/adc/ti-ads1015.c b/drivers/iio/adc/ti-ads1015.c index f92ec5941c47..3c78d85321e0 100644 --- a/drivers/iio/adc/ti-ads1015.c +++ b/drivers/iio/adc/ti-ads1015.c @@ -11,6 +11,7 @@ * * 0x4B - ADDR connected to SCL */ +#include #include #include #include @@ -39,14 +40,7 @@ #define ADS1015_LO_THRESH_REG 0x02 #define ADS1015_HI_THRESH_REG 0x03 -#define ADS1015_CFG_COMP_QUE_SHIFT 0 -#define ADS1015_CFG_COMP_LAT_SHIFT 2 -#define ADS1015_CFG_COMP_POL_SHIFT 3 -#define ADS1015_CFG_COMP_MODE_SHIFT 4 -#define ADS1015_CFG_DR_SHIFT 5 #define ADS1015_CFG_MOD_SHIFT 8 -#define ADS1015_CFG_PGA_SHIFT 9 -#define ADS1015_CFG_MUX_SHIFT 12 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0) #define ADS1015_CFG_COMP_LAT_MASK BIT(2) @@ -408,15 +402,15 @@ int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) dr = data->channel_data[chan].data_rate; mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | ADS1015_CFG_DR_MASK; - cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT | - dr << ADS1015_CFG_DR_SHIFT; + cfg = FIELD_PREP(ADS1015_CFG_MUX_MASK, chan) | FIELD_PREP(ADS1015_CFG_PGA_MASK, pga) | + FIELD_PREP(ADS1015_CFG_DR_MASK, dr); if (ads1015_event_channel_enabled(data)) { mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK; - cfg |= data->thresh_data[chan].comp_queue << - ADS1015_CFG_COMP_QUE_SHIFT | - data->comp_mode << - ADS1015_CFG_COMP_MODE_SHIFT; + cfg |= FIELD_PREP(ADS1015_CFG_COMP_QUE_MASK, + data->thresh_data[chan].comp_queue) | + FIELD_PREP(ADS1015_CFG_COMP_MODE_MASK, + data->comp_mode); } cfg = (old & ~mask) | (cfg & mask); @@ -427,7 +421,7 @@ int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) data->conv_invalid = true; } if (data->conv_invalid) { - dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT; + dr_old = FIELD_GET(ADS1015_CFG_DR_MASK, old); conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]); conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]); conv_time += conv_time / 10; /* 10% internal clock inaccuracy */ @@ -758,8 +752,8 @@ static int ads1015_disable_event_config(struct ads1015_data *data, ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, ADS1015_CFG_COMP_QUE_MASK, - ADS1015_CFG_COMP_DISABLE << - ADS1015_CFG_COMP_QUE_SHIFT); + FIELD_PREP(ADS1015_CFG_COMP_QUE_MASK, + ADS1015_CFG_COMP_DISABLE)); if (ret) return ret; @@ -999,19 +993,20 @@ static int ads1015_probe(struct i2c_client *client) unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK; unsigned int cfg_comp = - ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT | - 1 << ADS1015_CFG_COMP_LAT_SHIFT; + FIELD_PREP(ADS1015_CFG_COMP_QUE_MASK, + ADS1015_CFG_COMP_DISABLE) | + FIELD_PREP(ADS1015_CFG_COMP_LAT_MASK, 1); switch (irq_trig) { case IRQF_TRIGGER_FALLING: case IRQF_TRIGGER_LOW: - cfg_comp |= ADS1015_CFG_COMP_POL_LOW << - ADS1015_CFG_COMP_POL_SHIFT; + cfg_comp |= FIELD_PREP(ADS1015_CFG_COMP_POL_MASK, + ADS1015_CFG_COMP_POL_LOW); break; case IRQF_TRIGGER_HIGH: case IRQF_TRIGGER_RISING: - cfg_comp |= ADS1015_CFG_COMP_POL_HIGH << - ADS1015_CFG_COMP_POL_SHIFT; + cfg_comp |= FIELD_PREP(ADS1015_CFG_COMP_POL_MASK, + ADS1015_CFG_COMP_POL_HIGH); break; default: return -EINVAL; -- 2.39.5