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[109.193.28.127]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49981b631c1sm44532245e9.14.2026.08.12.16.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Aug 2026 16:13:35 -0700 (PDT) From: Marek Czernohous To: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Danilo Krummrich , Lyude Paul , David Airlie , Simona Vetter , Ben Skeggs Subject: [PATCH v3 3/4] drm/nouveau/fifo/nv04: filter benign CACHE_ERROR from Mesa NV50 bind probe Date: Thu, 13 Aug 2026 01:13:29 +0200 Message-ID: <20260812231330.705425-4-mczernohous@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260812231330.705425-1-mczernohous@gmail.com> References: <20260812231330.705425-1-mczernohous@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Marek Czernohous The Mesa userspace driver issues a method-0x0060 / data-0xbeef02xx binding probe that ends up triggering CACHE_ERROR in the PFIFO interrupt handler. The probe is harmless and recovers cleanly, but it is reported at error level, so it shows up in dmesg on session start. Filter that specific pattern down to debug level so dmesg stays clean while real CACHE_ERROR conditions are still logged at error level. The test is on the method and data pattern alone, not on the chip family, so it applies wherever nv04_fifo_intr() is the handler, that is nv04 through g98. That is deliberate rather than an oversight: a false positive would need userspace to write exactly 0xbeef02xx to method 0x0060, and the probe itself comes from the shared nouveau Gallium code rather than from anything NV50 specific. Say so here so the narrower wording of the subject is not read as a chip gate. Evidence: 99 occurrences across three logs from a second, independent MCP79/MCP7A machine running 7.0.10 and 6.12.90, under both Xorg and Wayland, with kwin and plasmashell named as the faulting clients. On my own reference machine the filter went in before the persistent kernel log did, so I cannot show a clean before and after from there. Assisted-by: Claude:claude-opus-5 Signed-off-by: Marek Czernohous --- .../gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 26 ++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index c4b8e567d86f..ab144c1bd9da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -327,12 +327,26 @@ nv04_fifo_intr_cache_error(struct nvkm_fifo *fifo, u32 chid, u32 get) if (!(pull0 & 0x00000100) || !nv04_fifo_swmthd(device, chid, mthd, data)) { - chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); - nvkm_error(subdev, "CACHE_ERROR - " - "ch %d [%s] subc %d mthd %04x data %08x\n", - chid, chan ? chan->name : "unknown", - (mthd >> 13) & 7, mthd & 0x1ffc, data); - nvkm_chan_put(&chan, flags); + /* + * Filter the benign Mesa bind probe: mthd 0x0060 with data + * 0xbeef02xx is a harmless userspace probe and does not + * indicate an actual error condition. The test is on the + * method and data pattern alone, so it applies on every + * chip that reaches this handler, not just on Tesla. + * Demote to debug to keep dmesg clean while still catching + * real CACHE_ERROR events. + */ + if ((mthd & 0x1ffc) == 0x0060 && + (data & 0xffffff00) == 0xbeef0200) { + nvkm_debug(subdev, "CACHE_ERROR - ch %d subc %d mthd %04x data %08x (benign, skipped)\n", + chid, (mthd >> 13) & 7, mthd & 0x1ffc, data); + } else { + chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); + nvkm_error(subdev, "CACHE_ERROR - ch %d [%s] subc %d mthd %04x data %08x\n", + chid, chan ? chan->name : "unknown", + (mthd >> 13) & 7, mthd & 0x1ffc, data); + nvkm_chan_put(&chan, flags); + } } nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); -- 2.54.0