From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B805476070 for ; Thu, 13 Aug 2026 12:57:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786625852; cv=none; b=iYrRbuvvjpNk1s7gHgnbyaxUYqbG8lgEGeLreQ7gHoYAE4PGUN9bppAYVE7+37H3juHiaQH9v/9WDy91sZDnzsRUEIPk9c0AFzKDKIX5ukm+CZeEPAQqQY8sUvWKghV14+geJNgM2fv42xctD1Kw6Xsg0UAWv/zDGtVgqoICY58= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786625852; c=relaxed/simple; bh=pT7C26Ldy9DHRXWPk1esuTAQ2YpR84dxOvIP8nSLG8g=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kSJGOs6CCZS0O8hXW6SC/AtEs7166+aBGd8LcpUHbsN8MoYzQrcdp/6NcUZl/AlYQTye5Js5cPGYDOO0jsf9ukshBeBQ0wrmz+37H/ucCCMQF8VEMzpfkKNp/GcVX8dOukXOWotVmLaMBIlm+iHIsPXgUd1Cd69r40/uGXz0TBI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=NM3qr4vm; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="NM3qr4vm" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4996c452e95so1563305e9.0 for ; Thu, 13 Aug 2026 05:57:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1786625849; x=1787230649; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:subject:cc:to:from:date:from:to:cc:subject :date:message-id:reply-to:content-type; bh=9fiE24ll9NgTLTpdzffi902DeMDS19T/hW1M1NBO/qc=; b=NM3qr4vmyxiJ0TeK7wi2HphIcsrhQjrlDq4GSUUn41N3qLbDVm+qSV6NiRLcbAwXrw ubbM4iWQ6csCXYCj+ZsVAf5dguW1jtfCszIA5aysNRADZk5FBU47+jZTW4aTe8qy9AHY b1v60kLYVVT2RivJQBYy7R5P1JmdoEg7mO6EqT4Qh+50fztVfzbenWUeHjr0O7ES94/G 56GFBj3jdQK5qR0RcWuMjMOFOT+u3bu5rHCjnV+01OmsfxnUA7ntA0yZ/K6MUehlGCrM xRoeYJgdHxQ35cvcjAsMrHfSwu6DRTprP/WaNbgPvUX3IR9H1lPl5XNzRqeur1dbXyie 7c1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786625849; x=1787230649; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:subject:cc:to:from:date:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=9fiE24ll9NgTLTpdzffi902DeMDS19T/hW1M1NBO/qc=; b=avDX+Kd3/NCWxKUl2fnEYI7UT+eECuLIv7/I243CDuxwchRS/XmDu03Ixh4n45MOpK 53uMJDDqWmXtsoyyS55LGOC84Rbq3il7+7M7MjQG/mRxD1LC5KkUzP4ailmLqTh+7dYy tB1euKlrafOM9cl6aGv1o/09QpFr3wsR8lpZhvvarU3YJV8GDyCs64Ka/pTsbVxbT2YT RxeY/OIrsbU+I7khYd2DE+wGykQd8K9XP0gPrtG97Dt1HxbuVW+urVxm9x5wojQ+7Op0 Ya+31Wm/3BHOCSVyBWz5LlKPrPveMrWFaCCTjQ+A/F6Ngg07t5JegzOWLTskrL//MXAM LnfA== X-Forwarded-Encrypted: i=1; AHgh+Rro/SHgd6MX7G4QBfFxVOD+s61q8d88XzUo2fBUle1nNAr/Nv2tHUdpjZQzL6TgeHdJTYF4dBRtbvAu8Kk=@vger.kernel.org X-Gm-Message-State: AOJu0Yw3cDghIDi9hrb3q3QnqkXBltbwRseISgNsmdkVoolAtHmxzUc8 l3VJ1jWcw+dseGOSKGCl+mWpnOkGf+dvxPoVC3gIC2p8pKWwhWkJuoTpMyvBpauuVH0= X-Gm-Gg: AR+sD12KBo+vQaxc7C8ogii7K0iVBGIFibXYORuyFy8VpvXDRFfSxND2m8N9yRq68sv qDsi9zZSHkjUBowgC8jpVf1M4lbXItok6Pfr1PHnnCIrX+V800WeKPqKIr/kMN8I6WUChoIYEAN JWRr6lnfILp6KWI5yMLRnL8Rm2t6r62ba9aMKlZnupL/0kARbr9VboG8YlJxMw96fhF0UEo62R8 xsGA4+WEClRS9gCEeVTrOOYpLymemyFlEYFGPuNuF41cAxMTnP3577/howjp2JRlZn08WIwhmxE b6lbw4eH6Q8+gFFZTjts3V7YL76zZSP6VpAOZg+OwdEqmwvLxhk5hsIHkP/+zkK8h2DZRizb0KT yPymnuZX0zbLDWDqWjO/W9dpsZand8HJAjr2Vc2hbfgLGb0ScgEBrCvxexWXccn2T8KjUcvB8jQ ce16bgDk9FXOZUcFxtxTiw6j3KW4a5PY6wRV0Ad4cllck/hZ/f69WB8DXvg63nFwDbXeIHFO+Wx YEhi5VJOHam1l3Yz5u9ZN48gkcOXIq8aLYR/TivqfAEahuq0p3VcH/YWpAXbLUF X-Received: by 2002:a05:600c:4fcc:b0:495:4126:1e55 with SMTP id 5b1f17b1804b1-4998264bdafmr33971245e9.2.1786625849332; Thu, 13 Aug 2026 05:57:29 -0700 (PDT) Received: from mordecai (dynamic-2a00-1028-83b8-1e7a-3010-3bd6-8521-caf1.ipv6.o2.cz. [2a00:1028:83b8:1e7a:3010:3bd6:8521:caf1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49981e4435bsm29534935e9.3.2026.08.13.05.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2026 05:57:28 -0700 (PDT) Date: Thu, 13 Aug 2026 14:57:25 +0200 From: Petr Tesarik To: "Mi, Dapeng" Cc: Sandipan Das , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Ravi Bangoria , Ananth Narayan Subject: Re: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug Message-ID: <20260813145725.22f21719@mordecai> In-Reply-To: <7078a9e7-6493-42b0-b297-ce174effdfb3@linux.intel.com> References: <7078a9e7-6493-42b0-b297-ce174effdfb3@linux.intel.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-suse-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 12 Aug 2026 10:37:20 +0800 "Mi, Dapeng" wrote: > On 8/6/2026 6:03 PM, Sandipan Das wrote: > > perf_event_print_debug() dumps the global control and status MSRs > > whenever x86_pmu.version >= 2, reading registers that exist only on > > Intel-compatible PMUs. This is not safe since x86_pmu.version is not > > Intel-specific and is now set by other vendors whose global registers > > use different addresses. > > > > As a first step, split perf_event_print_debug() in two. The register > > dump moves into a new common helper, x86_pmu_print_debug(), leaving > > perf_event_print_debug() to handle the preamble and dispatch to an > > optional x86_pmu::print_debug method. This lets each vendor-specific > > PMU dump its own global state before chaining into the common helper. > > PMUs that do not implement the method, such as those with > > x86_pmu.version < 2, get the common helper alone. > > > > No functional change intended. > > > > Signed-off-by: Sandipan Das > > --- > > arch/x86/events/core.c | 29 ++++++++++++++++++++++------- > > arch/x86/events/perf_event.h | 4 ++++ > > 2 files changed, 26 insertions(+), 7 deletions(-) > > > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > > index af0b67ffb43d..17dc53a62378 100644 > > --- a/arch/x86/events/core.c > > +++ b/arch/x86/events/core.c > > @@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, int flags) > > perf_event_update_userpage(event); > > } > > > > -void perf_event_print_debug(void) > > +void x86_pmu_print_debug(int cpu) > > { > > u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; > > unsigned long *cntr_mask, *fixed_cntr_mask; > > @@ -1566,17 +1566,11 @@ void perf_event_print_debug(void) > > u64 pebs, debugctl; > > int cpu, idx; > > > > - guard(irqsave)(); > > - > > - cpu = smp_processor_id(); > > cpuc = &per_cpu(cpu_hw_events, cpu); > > cntr_mask = hybrid(cpuc->pmu, cntr_mask); > > fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); > > pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); > > > > - if (!*(u64 *)cntr_mask) > > - return; > > - > > if (x86_pmu.version >= 2) { > > rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); > > rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); > > @@ -1622,6 +1616,27 @@ void perf_event_print_debug(void) > > } > > } > > > > +void perf_event_print_debug(void) > > +{ > > + struct cpu_hw_events *cpuc; > > + unsigned long *cntr_mask; > > + int cpu; > > + > > + guard(irqsave)(); > > + > > + cpu = smp_processor_id(); > > + cpuc = &per_cpu(cpu_hw_events, cpu); > > + cntr_mask = hybrid(cpuc->pmu, cntr_mask); > > + > > + if (!*(u64 *)cntr_mask) > > + return; > > + > > + if (x86_pmu.print_debug) > > + x86_pmu.print_debug(cpu); > > + else > > + x86_pmu_print_debug(cpu); > > The logic looks good, but better change this to the static_call() just like > other x86_pmu callbacks. It eliminates the branch prediction cost. Thanks. Is it worth the extra complexity for code that is used only by SysRq debugging? Of course, if it's trivial, let's do it anyway. Petr T