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Thu, 13 Aug 2026 10:02:08 -0700 From: Besar Wicaksono To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , "Besar Wicaksono" Subject: [PATCH 2/2] perf vendor events arm64: Fix Tegra410 Olympus event 0x0197 Date: Thu, 13 Aug 2026 17:01:55 +0000 Message-ID: <20260813170155.1156593-3-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260813170155.1156593-1-bwicaksono@nvidia.com> References: <20260813170155.1156593-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC5:EE_|CH0PR12MB8577:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ef40ab9-6d35-4204-fb3e-08def95caafb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|23010399003|376014|7416014|82310400026|921020|6133799003|10067099003|56012099006|11063799006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vQjVy6RVu4cLW2zc5g08BRwg2nFxSy35pZrpKxVdJAbAIx1j+6IHfUr2zQf5pY3gD6hXjQXuh/MhmZO9T0AzGhpA5S+QUih/zgvZrNJJY2GzzZcs4lwaGM7zdfH/uXCNdRDjhGCCAPGVTTT93vZs0FbUIUElC3o+SbBuEPFZRf0XZHmkQRGQAyknA/CnYXoy0Sm8SyL6pf6V6bDlguIE3GQiH0W7djlXj7P5vbNT2uLRtTArdiGflyyv7Ddmr+Mn5f2vJKgwModUIdkEEqRSUr8laA8puzkzuVuWzB9I//G57srYQGRnhq/1kdKcvoTB2eUzBei0FwU9xb/sl4BzmDaxZgqyhZNk8FK3/cAHpOcYDuPdDbKOd14S5l6kaDYjGymNILBJ9+eTb0bDNbpxAQZSAcyCiZ2BIIvn1eu6xm/2jiJy8ijKFT8YVjK35gUT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2026 17:02:33.2772 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ef40ab9-6d35-4204-fb3e-08def95caafb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8577 The name and description for NVIDIA Tegra410 Olympus implementation-defined event 0x0197 incorrectly indicate a TXREQ limit between one quarter and one half. Correct them to describe a TXREQ limit below one half. Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events") Signed-off-by: Besar Wicaksono --- tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json index 8ff87d844e52..e1b45cc33b18 100644 --- a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json @@ -316,8 +316,8 @@ }, { "EventCode": "0x0197", - "EventName": "TXREQ_LIMIT_1QUARTER_CYCLES", - "PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 1/4 of the L2_TQ_SIZE and 1/2 of the L2_TQ_SIZE." + "EventName": "TXREQ_LIMIT_BELOW_HALF_CYCLES", + "PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 0 and 1/2 of the L2_TQ_SIZE." }, { "EventCode": "0x019d", @@ -517,7 +517,7 @@ { "EventCode": "0x01cc", "EventName": "TXREQ_LIMIT_COUNT_CYCLES", - "PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_1QUARTER_CYCLES." + "PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_BELOW_HALF_CYCLES." }, { "EventCode": "0x01ce", -- 2.43.0