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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-320ea804233sm1062280eec.26.2026.08.14.00.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 00:32:02 -0700 (PDT) From: Hardeep Sharma Subject: [PATCH v2 00/15] Add initial support for Qualcomm Kuno SoC Date: Fri, 14 Aug 2026 13:01:31 +0530 Message-Id: <20260814-kuno-soc-support-v2-0-3079794f0f73@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAFTEfmoC/32NwQ6CMBBEf4Xs2ZLSKKIn/8NwKO0iVelilxIN4 d8tePcyyUtm3szAGBwynLMZAk6OHfkEapeB6bS/oXA2MSipSlnJk3hET4LJCI7DQGEUhdVNpUq LsmkhzYaArXtvymv9Y47NHc24etZG53ik8Nk+p2Lt/dFPhZDigBIt7rU0R3Uh5vwV9dNQ3+cpo F6W5QtM1QZVyQAAAA== X-Change-ID: 20260809-kuno-soc-support-1dab826de0bf To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Taniya Das , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Mukesh Savaliya , Dmitry Baryshkov , Bartosz Golaszewski X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786692713; l=5037; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=rtXTm0sNcVUQHP6jphCaU+mu+w6xi+uhAxczIqaG98E=; b=fUkvttIUx9VCeWiaW8i5QCky33IAmVohtGKSDZr78CLMXqmKNpCHYfU1KEQLV8FLetJGjWP5J 3ll8FB9xdhtAdIfmrCb/Iua1Pv0CIwTO5xFkvvbomvSJc4M5okPPa4Y X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Authority-Analysis: v=2.4 cv=K4MS2SWI c=1 sm=1 tr=0 ts=6a7ec473 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=kp1mlcltsySZhJOGRSoA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA1OCBTYWx0ZWRfX12EjAyoOVqHo B7W8JB98divK254R9UbbTZy6O+ZDdsA8dhhVjdibx1ATyVYBESYGpOvLFDS2MYiGquq+ppbLvf3 OwT3+NIPwTYqhsxqyecUAYe5TXfTP7ttSEd68OcAq96lbFt02OCs5Zs537R5MgUp5NHUrsrZYBt U1V+MAUyYVOCoRLXRC3ChkYjdUSTpS7xdc5UDMNCsFD2MoJt2rvEX1Y4VugPt9wW8U7dhEITAwy B6c7sx7Dxovmrb9caD8QxzipOW2mRZVh3o22Cdg2U2016jCrIwfVBVkPi8NtsDm8GV2sGQbiJT0 k/E08fyVgk+2J1F10o3zFIzQi1pulKr3fVxjaUGA2CoQtiXZDubrEww3qRh7Qk9BpXU7fuO/4f1 u5IdudbYPgS5rd2aSPAMndkoWmF6aoZz9ppDL1o3mjiTp8o08J4+Zqbd+EWm/j5ChSlchWGgeVL y1+Q+I/DZVwT0CnvBIA== X-Proofpoint-GUID: s3CENT8cyb14cusIpgbmWdxaEPvaSAKf X-Proofpoint-ORIG-GUID: s3CENT8cyb14cusIpgbmWdxaEPvaSAKf X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA1OCBTYWx0ZWRfX7ZY0QdVB64el Q+O1odd97up4yxuPr4YtrVUTrfPSFs5LuWKANjKgRpJ90R8OZQNpKD8VPtdzQbSN7NQ2bO7tfGU FBvl8Cvp3XFDlQBwdOtIohj6qh1RKGI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_02,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140058 This series adds initial support for the Qualcomm Kuno SoC and the Kuno IDP reference board. Kuno is a 32-bit ARM (Cortex-A7) Qualcomm platform. This series brings up the essential SoC infrastructure required to boot to a serial console: - Global Clock Controller (GCC) and RPMh clock controller - RPMh power domains - Interconnect (NoC) provider - TLMM pin controller - PDC interrupt controller and SCM firmware interface - Devicetree for the SoC and the Kuno IDP board The soc: qcom: geni-se patch allows the GENI serial engine driver to be selected on 32-bit ARM Qualcomm SoCs, which the debug UART console depends on. Signed-off-by: Hardeep Sharma --- Changes in v2: - Addressed v1 review feedback: - Reworked soc: qcom: geni-se commit message; dropped the Fixes: tag. - Reworded dt-bindings commit messages to the "Document X for the Qualcomm Kuno SoC" one-liner form. - Canonicalized copyright headers on interconnect binding / driver / NoC ID header to the single-line Qualcomm Technologies form. - Dropped unused from the interconnect driver. - Fixed MODULE_DESCRIPTION casing "KUNO" -> "Kuno" in the interconnect driver. - Extended interconnect binding to optionally allow up to four QoS AHB clocks (matches sdx75/glymur shape). - Cleaned up brace/space style in gcc-kuno.c to match peer clock drivers. - Reworked initial DTS: moved idle-states / domain-idle-states inside cpus{}, wrapped fixed clocks in a clocks{} container with peer node names (xo-board, sleep-clk), dropped the pcie_pipe_clk fixed-clock stub (the GCC 4th clock now uses <0> in DTS to match the sdx75 idiom; the YAML example uses a named placeholder), dropped the RPMHPD_CX power-domain reference on GCC (Kuno GCC has no GDSCs / no corner votes / no pm_runtime, so the reference was inert), and added a bootloader hand-off comment on the memory node. - Collected Acked-by / Reviewed-by tags from v1. - Link to v1: https://lore.kernel.org/all/20260809-kuno-soc-support-v1-0-5e0ede4a0c72@oss.qualcomm.com/ --- Hardeep Sharma (15): soc: qcom: geni-se: allow selection on 32-bit ARM Qualcomm SoCs dt-bindings: power: rpmpd: Document Kuno RPMh power domains pmdomain: qcom: rpmhpd: Add power domains for Kuno dt-bindings: clock: qcom,rpmhcc: Add Kuno RPMh clock controller clk: qcom: clk-rpmh: Add support for Kuno RPMh clocks dt-bindings: interconnect: Add Qualcomm Kuno NoC interconnect: qcom: Add Kuno interconnect provider driver dt-bindings: pinctrl: qcom: Add Kuno TLMM pinctrl: qcom: Add Kuno pinctrl driver dt-bindings: clock: qcom: Add Kuno Global Clock Controller clk: qcom: Add Global Clock Controller driver for Kuno dt-bindings: interrupt-controller: qcom,pdc: Add Kuno compatible string dt-bindings: firmware: qcom,scm: Document SCM on Kuno SoC dt-bindings: arm: qcom: Document Kuno IDP board ARM: dts: qcom: Add initial device tree for Kuno SoC .../devicetree/bindings/arm/qcom-soc.yaml | 4 +- Documentation/devicetree/bindings/arm/qcom.yaml | 5 + .../devicetree/bindings/clock/qcom,kuno-gcc.yaml | 50 + .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + .../devicetree/bindings/firmware/qcom,scm.yaml | 1 + .../bindings/interconnect/qcom,kuno-rpmh.yaml | 82 ++ .../bindings/interrupt-controller/qcom,pdc.yaml | 1 + .../bindings/pinctrl/qcom,kuno-tlmm.yaml | 109 ++ .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + arch/arm/boot/dts/qcom/Makefile | 1 + arch/arm/boot/dts/qcom/qcom-kuno-idp.dts | 25 + arch/arm/boot/dts/qcom/qcom-kuno.dtsi | 419 ++++++ drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rpmh.c | 15 + drivers/clk/qcom/gcc-kuno.c | 1438 ++++++++++++++++++++ drivers/interconnect/qcom/Kconfig | 13 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/kuno.c | 977 +++++++++++++ drivers/pinctrl/qcom/Kconfig.msm | 11 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-kuno.c | 796 +++++++++++ drivers/pmdomain/qcom/rpmhpd.c | 16 + drivers/soc/qcom/Kconfig | 1 - include/dt-bindings/clock/qcom,kuno-gcc.h | 95 ++ include/dt-bindings/interconnect/qcom,kuno.h | 89 ++ 26 files changed, 4161 insertions(+), 3 deletions(-) --- base-commit: 28d012efb4327f9c75d5e042a7c91e9a542efa98 change-id: 20260809-kuno-soc-support-1dab826de0bf Best regards, -- Hardeep Sharma