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[86.96.6.50]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49989ae9618sm1475095e9.13.2026.08.13.23.08.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2026 23:08:31 -0700 (PDT) From: Abid Ali Date: Fri, 14 Aug 2026 06:07:53 +0000 Subject: [PATCH net-next v4 1/3] net: stmmac: enable MAC rx/tx after DMA start Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260814-stmmac-rx-fifo-block-v4-1-1951fd3d33b7@gmail.com> References: <20260814-stmmac-rx-fifo-block-v4-0-1951fd3d33b7@gmail.com> In-Reply-To: <20260814-stmmac-rx-fifo-block-v4-0-1951fd3d33b7@gmail.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Russell King , Qingfang Deng , Maxime Chevallier Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Abid Ali X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786687705; l=2204; i=dev.taqnialabs@gmail.com; s=20260425; h=from:subject:message-id; bh=+DFF/LlKrj++mSfnje5JBkkLPuLJ0Z7cXJdpEeYpMoI=; b=7dmhLiBOgS0G/4/VZZyzW/fGUA2YSWzXKrxly684D4wqxf4gGB4SxH9/fcczyumvvs0b213FX M51iz7my+rAD0uK9HgHPV0/GD4hJngQzMHpTB7Ew9B6G62L5EMXOxHY X-Developer-Key: i=dev.taqnialabs@gmail.com; a=ed25519; pk=4Syx51HH/MOySSUpi79M2ToLOdwt1yiNb338eKZBJNk= When the MAC receiver is enabled before the DMA channels are started, incoming frames fill the MTL FIFO with no DMA engine to drain it. If the PHY/Switch is already up at this point, and there is inflow of packets towards EMAC, the per-queue FIFO overflows within this window. Once the FIFO is full, the MTL read controller goes idle and never retries delivery even if the DMA comes alive later on. This behaviour happens due to enabling the MAC RX path before the DMA setup is ready, and any delay between these events increases the chances of blocking the rx path permanently. The EMAC should only accept packets after the DMAs are enabled. Signed-off-by: Abid Ali --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index b2b7d0242dd3..b9d5d4aabf42 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3685,9 +3685,6 @@ static int stmmac_hw_setup(struct net_device *dev) priv->hw->rx_csum = 0; } - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - /* Set the HW DMA mode and the COE */ stmmac_dma_operation_mode(priv); @@ -3743,6 +3740,9 @@ static int stmmac_hw_setup(struct net_device *dev) /* Start the ball rolling... */ stmmac_start_all_dma(priv); + /* Enable the MAC Rx/Tx */ + stmmac_mac_set(priv, priv->ioaddr, true); + phylink_rx_clk_stop_block(priv->phylink); stmmac_set_hw_vlan_mode(priv, priv->hw); phylink_rx_clk_stop_unblock(priv->phylink); @@ -7184,12 +7184,12 @@ int stmmac_xdp_open(struct net_device *dev) hrtimer_setup(&tx_q->txtimer, stmmac_tx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); } - /* Enable the MAC Rx/Tx */ - stmmac_mac_set(priv, priv->ioaddr, true); - /* Start Rx & Tx DMA Channels */ stmmac_start_all_dma(priv); + /* Enable the MAC Rx/Tx */ + stmmac_mac_set(priv, priv->ioaddr, true); + ret = stmmac_request_irq(dev); if (ret) goto irq_error; -- 2.43.0