From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1615543F8BA for ; Fri, 14 Aug 2026 10:18:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786702733; cv=none; b=DAT4Og5v1q+srPogJn9PLh5yt/rdaR3bTtGb7Qgkb0s2LyfpqyurEQjWIJgKF8jk4DCpp28P6LBdMY1PTeqRahsDUzRU4D3t6KApWQcNVV0LY0VaWdTeV/q0Ox9vB2R6FhKLAq9cjaN0TU9wVVku26fYQvP1wkGiu3YXHmd3zrc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786702733; c=relaxed/simple; bh=GCnr4Mvm18woqcPyatGz9lyWobnOtJmYTMXDBVkkUVw=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=Z2M46MlqduvXfvbJqA3G2ZZIuJuxrIlNLBEpJ96VtvH7TZBwgSlb3PW4fpymDWOPxYIzNQF9dU8du0Z6cuU1/kcrF4RP/fChTfChxqeHBxomHCt4z2JoV1V7SS6bakwvlqmWDLJQZzdXLzmd6i2fl5aW4O76IF4plQ7FQabYVYk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FSRNdY5c; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FSRNdY5c" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2cc7e86e7aeso9334535ad.2 for ; Fri, 14 Aug 2026 03:18:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786702721; x=1787307521; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to:content-type; bh=SoVS6TyvWyTEmYUl+BaMNjP58PtMCPWRwsnVl6nfaY0=; b=FSRNdY5cUjftjEXHR6nwlsxaOEKsW1rKBmmdNZNYZbNET0taa+WJR9UkLTRgm9DTVs BufwmboZzKapO6Hn/oo2CIgszxvWpxKhLjBEVgMjdzPuxqMS6hrXfyaCzzNTWzn/Mlrq tzVQI6nqtcl1kV8hY/EFFSPrE8okFLZ6X7IsQr+Zvv3Sz7FptqEdgsMpb4xl41wlqjA6 18EVEwe853+2e7s2XwCgMeVMjxCLMDksJtagBy8JLdiZoJ6tka2wYLchOYWExqqO9Vaf 6mbqm8406Mi3ssn3ejybO36zvNOvNHoS2m23NfKrM2vQKF9WNnayZWzUTwG49OkbydRq YChg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786702721; x=1787307521; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=SoVS6TyvWyTEmYUl+BaMNjP58PtMCPWRwsnVl6nfaY0=; b=FF/6JPZXEV1tyzz7oCZybETnHnDzAqajm18gFp1BE9TrcMr5KBvp1e3KshalqFvMfw j/CSpqJvNrzvtdA/NYh11G+cERQH5wcru92wRFjemHhkxKL79lwQO6lItvW8vDN/wJ1T yUuEabqEKXd70coVcn146VcQWy4Yr8gDh4MzMLdwGAFLsNcZH70oex9bqUH5cM+6y3e6 hVD9A/78Zz5WmhdUAavRX2Q/haKl9OQqJBod6VpR9F8xCD0iYefKb0nfBDYX86Mu/kvl AO7eQdHoIsETooOM9XmHeKOjO0fDcjWmkcJ5BBZo8zQgdc97XahEYfwKV2e9vAV0AgRq CmFQ== X-Forwarded-Encrypted: i=1; AHgh+RqAkBU17k5ExZs7/PfjL18TIansYEpgOtMcyN6OF0yB5zeW6kTV+MHhi2ECQzIU+KgC9Pi1gvIOCZ10JoM=@vger.kernel.org X-Gm-Message-State: AOJu0YxB4ckkttY+41mAAHSavUhJz7QMf+eoilzjTsLE7qFMszrzgGhO nn8RFJ/2RiC/WFUiyjonCW38/44lpjGdIU4peGLQdKS8poVxtMSQM4xC X-Gm-Gg: AR+sD12jZkz5RKEGplX+SnCoCeZYr+DGNoHgUNZmEB3RZPwXYinr/t/WNno8PWuWK/g XwVodzMdtcT31hBt4IruZ0+SOnXaKm9gm58mvq7905WVRpHS2+ZxbNbhUsdRb5DYGuW6AcFtT8R 0rLdEoD+B7osYFWj3ucbZPrnpN6hFqhj1S7iLUgBn6Fgu02Dbwme+v6EmX6c/ARqurP9CiSzo8C 2B+YluMVv7DyAsl7cJ1BO3NY+fxuhQVYgaSc8kVgGtj6wU4dO4s4Pe2Mv9K+lJg6croQKlE52+w oCjWQF8Ypu+OBcUpdOLAWdnV6RM4N4dgZKoSlYKCI/8YyEvfPRal5Hy8yf9ZeeuA5XCQnf1kvTx Asnczz4RhGNWhMFTtbqkkGom2T8sBbxhDlKjQL+YosHv3Ovn/+6nX/98J3KMD91toSLVh3op8Y4 YyLOTwc4Czf5syWxxDGfiNWv3cn41gQOJ6R3UKEYe7aMu4Tbyw+UXOk0FrjyOOoMeGDGtEGnKdU M+9i84= X-Received: by 2002:a17:903:360c:b0:2ca:b8fd:f31 with SMTP id d9443c01a7336-2d3b0d5e37amr51097825ad.15.1786702720815; Fri, 14 Aug 2026 03:18:40 -0700 (PDT) Received: from inhnjlux1020.ls.ege.ds ([2406:b400:53:97cb:44f1:865e:4c69:6423]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d3aebc81a6sm7393685ad.72.2026.08.14.03.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 03:18:39 -0700 (PDT) From: Udaya Kiran Challa To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, me@brighamcampbell.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Udaya Kiran Challa , Conor Dooley Subject: [PATCH v3] spi: dt-bindings: microchip,pic32mzda-sqi: Convert to DT schema Date: Fri, 14 Aug 2026 15:47:33 +0530 Message-Id: <20260814101733.46406-1-challauday369@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert Microchip PIC32 Quad SPI controller devicetree binding from legacy text format to DT schema. Reviewed-by: Conor Dooley Signed-off-by: Udaya Kiran Challa --- Changelog: Changes since v2: - Change maintainer to SPI subsystem maintainer Link to v2: https://lore.kernel.org/all/20260625060903.14661-1-challauday369@gmail.com/ Changes since v1: - Drop maxItems and add items list in 'clocks' property - Remove unsed label from example node Link to v1: https://lore.kernel.org/all/20260624061329.130468-1-challauday369@gmail.com/ --- .../bindings/spi/microchip,pic32mzda-sqi.yaml | 55 +++++++++++++++++++ .../devicetree/bindings/spi/sqi-pic32.txt | 18 ------ 2 files changed, 55 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml delete mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt diff --git a/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml b/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml new file mode 100644 index 000000000000..f684c359a199 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/microchip,pic32mzda-sqi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32MZDA Quad SPI controller + +maintainers: + - Mark Brown + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: microchip,pic32mzda-sqi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SPI source clock + - description: SQI register interface clock + + clock-names: + items: + - const: spi_ck + - const: reg_ck + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi@1f8e2000 { + compatible = "microchip,pic32mzda-sqi"; + reg = <0x1f8e2000 0x200>; + interrupts = <169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>; + clock-names = "spi_ck", "reg_ck"; + }; diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt deleted file mode 100644 index c82d021bce50..000000000000 --- a/Documentation/devicetree/bindings/spi/sqi-pic32.txt +++ /dev/null @@ -1,18 +0,0 @@ -Microchip PIC32 Quad SPI controller ------------------------------------ -Required properties: -- compatible: Should be "microchip,pic32mzda-sqi". -- reg: Address and length of SQI controller register space. -- interrupts: Should contain SQI interrupt. -- clocks: Should contain phandle of two clocks in sequence, one that drives - clock on SPI bus and other that drives SQI controller. -- clock-names: Should be "spi_ck" and "reg_ck" in order. - -Example: - sqi1: spi@1f8e2000 { - compatible = "microchip,pic32mzda-sqi"; - reg = <0x1f8e2000 0x200>; - clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>; - clock-names = "spi_ck", "reg_ck"; - interrupts = <169 IRQ_TYPE_LEVEL_HIGH>; - }; -- 2.34.1