From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-43171.protonmail.ch (mail-43171.protonmail.ch [185.70.43.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B89033FE0A for ; Fri, 14 Aug 2026 11:20:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.171 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786706459; cv=none; b=oCcZcnpWyq0yhfAvGXC3QgbUZGFMomeHnmlKD2AH76/IFswh7km504te1X0fxiANNNkac9XSIkk4tcTuUZ/Iu4GE1hzX/fqLBy10M0kyE07s0EbXU6kkH9UgaSnZacX+PKiEQBbJp0X0n7+LT0ttlFso18zeq0/1CeZKDzHhmmw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786706459; c=relaxed/simple; bh=2DkG2Gs65Mg8lCl+FvaDdG2zeJ3pZ4fCTYIVPzzv+Ro=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C4oJIzTlnZ356ElomNZGeOQEDX0pSllsTdii/ELSD+kMVHKEd0sCLd+ETOWLI3ZA/C111+nxUg+2TUBs426XJTohL5pJrY1D8l7fMyvY0jfeeV9yyh/zJHOgmfeZXk4AqBJODTdTts2Ofj+SRd5509Zpd/LVl96U81ncpqEcNIY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev; spf=pass smtp.mailfrom=onurozkan.dev; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b=RM6wIpCJ; arc=none smtp.client-ip=185.70.43.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=onurozkan.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=onurozkan.dev header.i=@onurozkan.dev header.b="RM6wIpCJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=onurozkan.dev; s=protonmail; t=1786706450; x=1786965650; bh=gZ/xY1sbSmHJCkms60/TkZPkt1U/i9ryG+oCm5UgYgs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=RM6wIpCJhmVGinbIi5+H+Iv8TmFW5a0Cu5+6zMVwUJwOuDQLX5I/uc3ATyUgU0JU/ k3fsvmLc+g+XY6JdGGNomq7AaqoO18kiVQ2EFwLUe6sS4+FaVzwudutV4zRT2YjYOs yoYB46EaIptWOKxrpVf/IXEhAYnaBS5oPTNxbLTDOyMwWZhTb1oP4+a8mRkDfyjBel jx+xcI8kla47FWQmR2sROKEgGaMBUuA0ONMJZ5Dsp7IGOG6IVmPOX4pzawM5ggYayX 82Zhmm0zBpPyNrTd53qfA8G7JzFBsxXLSArwYbZJprW8pQ/35smnbyKQhGSQBSwiKd NnLZOrvNc/p4Q== X-Pm-Submission-Id: 4hM0CM0VVkz2Sd4C From: =?UTF-8?q?Onur=20=C3=96zkan?= To: Daniel Almeida Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, dakr@kernel.org, aliceryhl@google.com, airlied@gmail.com, simona@ffwll.ch, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu Subject: Re: [PATCH v4 3/3] drm/tyr: add GPU reset infrastructure Date: Fri, 14 Aug 2026 14:20:39 +0300 Message-ID: <20260814112045.72877-1-work@onurozkan.dev> X-Mailer: git-send-email 2.51.2 In-Reply-To: References: <20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev> <20260813-tyr-reset-impl-v4-3-b36fcd0805b2@onurozkan.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, 13 Aug 2026 20:25:15 -0300=0D Daniel Almeida wrote:=0D =0D > Hi Onur,=0D > =0D > Can we move the iomem to the HwGate and get rid of its Arc? This way we= =0D > ensure that all hardware access must consider the possibility of an ongoi= ng=0D > reset by having each component that needs hardware access hold an Arc=0D > instead. Perhaps we can even broaden this to "hardware must be powered on= " at=0D > some point in the future.=0D =0D Sounds good to me, will do that in v5.=0D =0D Regards,=0D Onur=0D =0D > =0D > Otherwise, this looks good to me. Let's wait for Alice too.=0D