From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mta1.migadu.com (out-232.mta1.migadu.com [95.215.58.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B88F5463B83 for ; Fri, 14 Aug 2026 11:45:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.232 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786707931; cv=none; b=Qt+cz0t6IMqei5LA/NGh6pKw7UExL196NRWmt2Sa+skiOdLaDwq+GL4dC+i38JAnxGL9uijnNjCaw+Vo589hOlxXLeSKbNAxtXBYYScMAunC9askY09YlLbBhckG7ArJvqknFaP+Ezp1nsgHOU1elJu+sDR8MXPyN7apod0/1XM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786707931; c=relaxed/simple; bh=GOT8taQt6/EQFiPSFOU6QPaJFvivwjZtCf7FY3zWtvw=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=nD7Fb6aKPoOaR8zw5U1xHY/tSYdrsoeAzteGvY2F9pDIwAZ4cWCaaLedNC+MphNJLqwnw7km05wid5AdIHoVbSn2XtLwaDt/jf2V9gFM9GBLSUSSG2JAuj9jwYv9DB1yNj7OBEghr0dy2NugpEW0MySShf7+RolOE1YcAiE+lnU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=dJ5BIi20; arc=none smtp.client-ip=95.215.58.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="dJ5BIi20" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=GOT8taQt6/EQFiPSFOU6QPaJFvivwjZtCf7FY3zWtvw=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1786707926; v=1; x=1787312726; b=dJ5BIi204qbL9joWj4vbh5NOkPKE9dGc+FEIk0tDnKwO/8anVKnbEyAl8e37fL8M38grg4J0 aJWDQ6E3PTjE07rXnqAt3v7/lYcHm3UdHavLkBsNwp2kSKX5Z/ytHuRW3lrnpatRKlgsFc9HQCe 3k1EvKHEhHSBMUpJ3GnNe/xA= X-Envelope-To: linux-kernel@vger.kernel.org Received: from localhost.localdomain (2408:823d:2011:2c0:e810:54f9:f0a3:99d) by smtp.migadu.com with ESMTPS id 7e7cb55356a33f08; Fri, 14 Aug 2026 11:45:26 +0000 X-Migadu-Flow: FLOW_OUT From: Jinyu Tang To: Anup Patel , Anup Patel , Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra , Paul Walmsley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Conor Dooley , Yong-Xuan Wang , Nutty Liu , Jinyu Tang , Jinyu Tang Subject: [PATCH v3 0/3] KVM: riscv: Add KVM_PRE_FAULT_MEMORY support Date: Fri, 14 Aug 2026 07:45:04 -0400 Message-ID: <20260814114507.583424-1-jinyu.tang@linux.dev> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds RISC-V support for the generic KVM_PRE_FAULT_MEMORY vcpu ioctl and enables the existing generic KVM selftest for RISC-V. KVM_PRE_FAULT_MEMORY lets userspace ask KVM to populate stage-2 mappings for a GPA range before running a vCPU that is expected to access that range. x86 already supports the ioctl; RISC-V currently falls back to normal first-touch G-stage faults. Patch 1 implements the RISC-V arch hook using the existing G-stage map path. Patch 2 fixes the RISC-V selftest page-table walker for Sv57, which can be selected as the default guest mode. Patch 3 enables pre_fault_memory_test for RISC-V. Changes in v3: - Retry internally when the map path returns success without a visible G-stage mapping, instead of exposing -EAGAIN. (Sashiko) Changes in v2: - Drop the per-test guest_modes_append_default() call from pre_fault_memory_test.c. RISC-V already initializes supported and default guest modes from kvm_selftest_arch_init(), which is called by the common kvm_selftest_init() constructor, as suggested by Sean. Jinyu Tang (3): KVM: riscv: Implement KVM_PRE_FAULT_MEMORY KVM: selftests: Add RISC-V Sv57 page table indexing KVM: selftests: Enable pre_fault_memory_test for RISC-V arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/gstage.c | 3 ++ arch/riscv/kvm/mmu.c | 42 +++++++++++++++++++ arch/riscv/kvm/vm.c | 1 + tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/include/riscv/processor.h | 6 +++ .../selftests/kvm/lib/riscv/processor.c | 2 + 7 files changed, 56 insertions(+) -- 2.43.0