From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FD923E3C74 for ; Fri, 14 Aug 2026 23:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786751918; cv=none; b=XAycU17uSYC6GGOKs51WBs959hNpodfnhF7xpGEUuK1KEEq0YrITrWicexFvvoGTAv+03Q/Kra96uTyxOib7qOzYV0IE018x26gtQloJT2deccBMqF7s4HQ60XOnyxCo+CcjjcJzuGb5m1NbJEM6k1UmD3ozfl+DrWbe8XSUNEs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786751918; c=relaxed/simple; bh=rpDJcw0ocB5viwX3/H3CW72TjZT8qLu3yYj3cTIRJrc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B/qnEUqCsDZbBsYrwXLojlIztIeKoI4z+DUB1qS6PSSxOtY7kkWPFODUIjClgqqtNFu+6pHZF/SO6QVCHgbdd5bRyTVwFjAN9JMfIN5YTALqmj61JyVt0hLGhUfQcifaTwdWzwBxpY+RIMQM2ZZ5t1Jr/KIKPak1t/UmXqx+e+8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=a5F+NzlQ; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="a5F+NzlQ" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4954dff6536so12381925e9.0 for ; Fri, 14 Aug 2026 16:58:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786751915; x=1787356715; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=IciWU/aDLaHcZt/8OhEMPCWAuQRlBMduwtoNidgedNY=; b=a5F+NzlQagdwWWqpOiOHdRA/LiQI4m9rv52d17l1q+n4V0dt1sdQYwNCeklZnfhs1A 0QslSsgJ5mdGDqQ//yo55/fyS6J2oMfuoI5jPRX0bmndIR5T4UP6Fh65Pzl/DorgRVpV QWz0cnORVFzugi5UwVLJHE/QfxVQ/hUbsm5Oi7qQb2Ttdeu+zAyO9btW+s6BrQc0/nL3 773wL57OyXd8sLYz2hJx0/xYvXvr1SGV1MPjE+ddauorjKw+3MMfDEl0ifLJDIgR3Fil vwk6i0hu2ARXHWfu7fCmCLYgJsvzLjzl72uN6CiwI0l17u3yKRTv+Faiu2HcksLWelys tnTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786751915; x=1787356715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=IciWU/aDLaHcZt/8OhEMPCWAuQRlBMduwtoNidgedNY=; b=RFrgEhHjHHf+wmqQ+upyPORXdPQz98zfWrnGp5YKUScZ1tQi7UMcX1+S7ZUejvkqfU 7TsTIfeH7h6youNvRrm3FO2tvsfBtYQjwQhEBEsouuVbMpmdTrGfE1fm81KfFzZ6+iKj XpqK8Y1q3Q9BaELHjZCA4/elM/CzSlYxhbU5FEoy7eT9JQgvKUtrv22oRYmMlUyF9hu9 luTbC1BTywJ8T/bnSatV+79mO/dhhoE+3xox9UCrzjsSbAt5r/80BXkvP3hlLEHVn8s7 xkc3vlidtvVpl14JvrLYp8bADrRQ0To5GZHxzySJpY2gNs9yCPP71awUutIZzK5oPisL OhcQ== X-Gm-Message-State: AOJu0YzN3wUPy9QiF4N8+feUxqkPp+u/6hH1wtYoc19dVPiRM2KR0l/l 7V5edlsBigpwZ+BqklBTISfMjF9syItPEVIYMHIYmuvZs+2tneDq/aW5ZlJXW03WoxY= X-Gm-Gg: AR+sD11pahlENNPQSos31Dt1qhv96GzmdlTMM/RvfJ1VbU0wyvm6w8urovWHTf8OIWB giSdZ0U/T6zyBFbIonOHQHv6EJmPKl7eF9s8NQoXrMHTGgFhd0bGieyAleuxgYuZYRQ0hs3IlGV eEpvoNst1O5cVNMkm+a6/c7iTeR8D5sRrevxaZNVxkv6WEEqBO6gbeDafWzv/lLiYdgsjJUH+dW lDZBr9v1l0yRucaPRm2mFzdehId4Bw/2JVdCYFyMueVsJBk+l1wp1CypUTk1ve7Q4frNqFSAc/a vbms7KVDuohoZjvp9CUxTKDq6TIsYxzwUV2BWh8QqF9r7iGodRNsbo+OE/uek7XVlXq5SzIey42 oG82R2kqBo9wV4hrbjjWgYavq5B6jliM0HWMVPyJSsrfPEiOIqzG02S6rEBaOUyNkpkZvEiGAMx T0w+v0QzndVZKolW8OEMUa8ZWqkw4MuLBvSPurag32hAzp4l7CJe98AM04IXxgRjCWH7DQ X-Received: by 2002:a05:600c:3b23:b0:499:8ae1:b900 with SMTP id 5b1f17b1804b1-4998ae1bb69mr69497395e9.12.1786751914839; Fri, 14 Aug 2026 16:58:34 -0700 (PDT) Received: from fedora ([5.31.134.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899753ccsm77751245e9.0.2026.08.14.16.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 16:58:34 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org, Mohamed Ahmed Subject: [PATCH 1/7] nouveau/disp: add GB20x HDMI vendor infoframe writer Date: Sat, 15 Aug 2026 03:56:59 +0400 Message-ID: <20260814235705.59132-2-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> References: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit GB20x (NVDisplay 5.0) reorganised the SF HDMI packet units and the legacy VSI unit at 0x6f0100 no longer exists. Per NVIDIA's published CA71 DISP_SF_USER class header, only three legacy units remain (AVI at +0x000, GCP at +0x040, ACR at +0x080), and vendor infoframes must instead be sent through the shared generic infoframe units at +0x130, which feed a 9-dword data FIFO at +0x3f0/+0x3f4. Add a VSI writer using the same programming sequence OpenRM uses on these chips (nvhdmipkt_C971.c, programAdvancedInfoframeC971()): disable the unit and wait for it to idle, clear the SENT status, write the packet through the data FIFO with a zero HB3 inserted after the three header bytes, then enable the unit for every-frame transmission during vblank. Generic unit 1 is used for the VSI, matching the slot assignment in NVIDIA's nvkms (NVHDMIPKT_TYPE_SHARED_GENERIC2, unit 0 is reserved for extended metadata packets and unit 2 for the HDR DRM infoframe, if those are wired up later). Signed-off-by: Mohamed Ahmed --- .../gpu/drm/nouveau/nvkm/engine/disp/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/gb202.c | 62 +++++++++++++++++++ .../gpu/drm/nouveau/nvkm/engine/disp/ior.h | 2 + 3 files changed, 65 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild index e1aecd3fe96c..98d6ca5ac311 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild @@ -27,6 +27,7 @@ nvkm-y += nvkm/engine/disp/gp102.o nvkm-y += nvkm/engine/disp/gv100.o nvkm-y += nvkm/engine/disp/tu102.o nvkm-y += nvkm/engine/disp/ga102.o +nvkm-y += nvkm/engine/disp/gb202.o nvkm-y += nvkm/engine/disp/udisp.o nvkm-y += nvkm/engine/disp/uconn.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c new file mode 100644 index 000000000000..8fd72bcb6f04 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2026 Valve Corp. + */ +#include "priv.h" +#include "ior.h" + +#include + +/* GB20x (NVD5.0) reorganised the SF HDMI packet units. The AVI unit is + * unchanged from GV100, but the legacy VSI unit is gone. Vendor infoframes + * are sent through the shared generic infoframe units instead. Register + * layout per NVIDIA's clc971.h/clca71.h, programming sequence per + * nvhdmipkt_C971.c:programAdvancedInfoframeC971(). + */ +void +gb202_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size) +{ + struct nvkm_device *device = ior->disp->engine.subdev.device; + const u32 hoff = head * 0x400; + /* Generic infoframe unit 1, the slot NVIDIA's driver uses for the VSI. */ + const u32 ctrl = 0x6f0138 + hoff; + u8 buf[36] = {}; + int i; + + /* Disable the unit and wait for it to go idle. */ + nvkm_mask(device, ctrl, 0x00000001, 0x00000000); + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, ctrl) & 0x00400000)) + break; + ) < 0) + return; + + if (!size) + return; + + /* Clear SENT status, and point the data FIFO at unit 1's slot. */ + nvkm_mask(device, ctrl, 0x00800000, 0x00800000); + nvkm_wr32(device, 0x6f03f0 + hoff, 0x00000001); + + /* The FIFO takes the raw packet, except that a zero HB3 is inserted + * after the three header bytes. A unit sends 36 bytes. + */ + size = min_t(u32, size, 31); + memcpy(buf, data, min_t(u32, size, 3)); + if (size > 3) + memcpy(&buf[4], (u8 *)data + 3, size - 3); + + for (i = 0; i < 36; i += 4) { + nvkm_wr32(device, 0x6f03f4 + hoff, buf[i + 0] | buf[i + 1] << 8 | + buf[i + 2] << 16 | buf[i + 3] << 24); + } + + /* No flip ID or scanline matching. */ + nvkm_wr32(device, 0x6f013c + hoff, 0x00000000); + + /* ENABLE | RUN_MODE=ALWAYS | LOC=VBLANK | OFFSET=1 | SIZE=0. */ + nvkm_wr32(device, ctrl, 0x00000041); + + /* Audio priority low (the init value). */ + nvkm_wr32(device, 0x6f03f8 + hoff, 0x00000002); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h index 3ba04bead2f9..8906fe8ef404 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h @@ -196,6 +196,8 @@ extern const struct nvkm_ior_func_hda gv100_sor_hda; void tu102_sor_dp_vcpi(struct nvkm_ior *, int, u8, u8, u16, u16); +void gb202_sor_hdmi_infoframe_vsi(struct nvkm_ior *, int, void *, u32); + int nv50_pior_cnt(struct nvkm_disp *, unsigned long *); int nv50_pior_new(struct nvkm_disp *, int); void nv50_pior_depth(struct nvkm_ior *, struct nvkm_ior_state *, u32 ctrl); -- 2.55.0