From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D2D93F8ED3 for ; Mon, 17 Aug 2026 10:55:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786964131; cv=none; b=aqDyr2QEFXBGFZ4au0oOKif/tRSCnZKyoT1CXyuBGiEpgGid9RjJ1uNiFyGmh9qKLPDlcYUV6KKnOyl7de48Ygs/BYBAuxYQbHYGYt742uXssnZLTR3BvfmZlWuzuSE119vBqnsITknjxIVhgVO34VlGMsuFSMD1n4Xg0p6E8vA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786964131; c=relaxed/simple; bh=oY/WPxJ7Hk/heY3LL7xfbLbJFoxIPUpFgoVBsoCjkik=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=StgJrHpG7B1rDkhrB4Wqog8WBC5O8CovXrbaPhqQ0bP6BNfyfEbhctQ+hySHZu1aByKmgrK0gZtYr12lLvFj/c2xjITpgxS8OqV6iFG7xkp8d9Ihi+R5+4HSjmaJIWlx9qU3U2EJZJrWIhlGTIVSdy3j73CPmGtEwN84cJ8oSRU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=X+ae67ja; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="X+ae67ja" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-49954b88fffso36671345e9.0 for ; Mon, 17 Aug 2026 03:55:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786964126; x=1787568926; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:subject:cc:to:from:date:from:to:cc:subject :date:message-id:reply-to:content-type; bh=9LRBFBAtx27EuSLkwrHlog8l1cdy3L7iJ6s4HbjypDE=; b=X+ae67jaemIqlvGRxEXGRjtoWXSQ14jiNnDwYE9NAPWNFQDKhzZa2BvbxmmHswmKMQ EEhiTg8IcAqu0H0skHDlhh7gRdn3eXL+PxTiO9vdVr/zI9901TSD73BmT3Hxz7Nd3gcu LOdhzz2ez3OMG/YDdRoioMNVEsa7lSWvaLNGxL9yUbXQX9CJDZ58kf82zqsqtZ3z5sbP 1k1LvLPD885bjZTCRom1hc4vmnEMUw9/5iPmni17EVSJ64vPIT0uYCKXvJuhCOpiIri2 xiOx0hutDe50dbC0tB5/VH9k1rFyFXkc/L05viA5lU32Dq8cr/uXP9jgVaduSXb/5bUT f0+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786964126; x=1787568926; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:subject:cc:to:from:date:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=9LRBFBAtx27EuSLkwrHlog8l1cdy3L7iJ6s4HbjypDE=; b=hwSWX0XIRLv/+4WcIT1zh6wequL1qKuChdeyTwHm78j+4QIj9H38OUuQOgDrUU7iVq pYWE9IraUvcFjyaENRW1LE9O1tuROnudYKVFiYsLsOa18EZELrpus3erNc+IvZ0+BBNz c9wKb7Zh8jId0X9/l0D2zk3NJPz7nmfJ1gu759lifZ9tAeZyO/avES3ryhEKYglQbGEV QIU7ERMa7OIGM9QYhfPSiXdUFu4msXMXFtNvHLn4VFdx7k13b1jfFmNpSkmp7WP/oUOw DvIsr/phkkm5TNm5Y9Nc+lmB4QXBodMtRhwp3Ep+r03WqUkel1F2njvnZpMQogczl3Er q1Ag== X-Forwarded-Encrypted: i=1; AHgh+RrI0/SzxD+3LcTOXMQQndztQgH+YdYIBHExJmEwaB4dZKmp6jzz4zmNAqTGMP/g2bOpqghaJ63HM0KXNCE=@vger.kernel.org X-Gm-Message-State: AOJu0YxnoJrSt4d9YSYYNYBW/UBVTo/CxdJtsN4SHZGdT/lqbsDJIVNX F+wYGKdJK6UO+L6q0BaKjgDMyBZiBiYVh+U9eOXJ1Q9N+brIhZb25nXv X-Gm-Gg: AR+sD11ecCTh3rCCBJC55mLxNPX9kiaek2CAAZttePIMNobh4HV1p+4ODuv5V6V4fRD exu6NZsZzFBqXIy85KhzEizEmffA34g7ODfncFbqr4eh0SzurMK2coLDgv0RTzGVTWM2nge2Sv/ K7+g8PtcllRrg8jiPIW8a442c6ZGU1pX3Gb04P5bAIbrJ/gT/ahwbZsaI2dl9bXBtPPpqDIgsPC RjpURhdRWlU67pAZj0vzhQiyLEVqly6ihGhzJ3CWnc2DfKXg9zJUz53Gxim/BJY5oyXruPKIKPH Fl5UQ5cIgN+pt6F1HCXtmItRDbXzjUglmwqPmlZkhjt4Uj59cYYlCKSvRnjQ6NfFmE7/Ergs2yd +iqL+cqzJr6kNesD3a8SY5Pp33X9i8QY5fJu/jMDKxA4xstWE5bu4dOW1Z8iLKTWKq4JjSlzmZw S0YYnhDK8l/J0QwAIGDRwFFx8VbOwpQWATZlhgu/fnwqYXkLF1f0YAtH2Qfclkafj9mQJZ2yaAs P544nzBO0pGEJHg/H8f99DVRw== X-Received: by 2002:a05:600c:628c:b0:499:87f3:a2a3 with SMTP id 5b1f17b1804b1-49987f3a33emr415143305e9.15.1786964125514; Mon, 17 Aug 2026 03:55:25 -0700 (PDT) Received: from pumpkin (82-69-66-36.dsl.in-addr.zen.co.uk. [82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499961098cdsm157881145e9.6.2026.08.17.03.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 03:55:25 -0700 (PDT) Date: Mon, 17 Aug 2026 11:55:23 +0100 From: David Laight To: Christoph Hellwig Cc: Eric Biggers , x86@kernel.org, linux-kernel@vger.kernel.org, linux-raid@vger.kernel.org, linux-crypto@vger.kernel.org, Herbert Xu , Taehee Yoo , netfilter-devel@vger.kernel.org, Pablo Neira Ayuso , Florian Westphal , Phil Sutter Subject: Re: [PATCH 0/6] x86: add missing vzeroupper instructions Message-ID: <20260817115523.7c6c646a@pumpkin> In-Reply-To: References: <20260815205750.169336-1-ebiggers@kernel.org> <20260816161450.05fd24f2@pumpkin> <20260816173159.GB2013@sol> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 17 Aug 2026 02:15:19 -0700 Christoph Hellwig wrote: > On Sun, Aug 16, 2026 at 10:31:59AM -0700, Eric Biggers wrote: > > As for kernel_fpu_begin(), no, it doesn't do vzeroupper. > > > > I do think that some years down the line, we'll drop the use of SSE in > > the kernel entirely. At that point, vzeroupper in kernel_fpu_end() > > would make sense. > > Or add kernel_avx_{begin,end} wrappers that include the vzeroupper > in kernel_avx_end. That would be a lot easier to use than the manual > vzeroupper in every modern user of in-kernel AVX. > You might want one in the start as well. I have a theory that the avx512 logic was added as a completely separate block. This meant it could be included in cpu for testing but disabled in any released to customers. (Or maybe the it is the original avx logic that used latches not in the normal register file.) A side effect is that different latches are used for the low bits of the registers - so when you change to/from avx512 the register contents have to be transferred between the blocks - adding latency. So if the wrong registers are live for the code you are going to execute the data has to be transferred across. There are also other effects as well. I found this link: https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html It is a few years old now (2020) but probably still relevant. A quick summary is that the first 256 or 512 bit instruction starts a 9us window where the cpu runs at 1/4 speed, for 512 bit that is followed by 11us where nothing happens at all. David