From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEAD837DE99; Mon, 17 Aug 2026 18:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786992089; cv=none; b=IbYagtBQSOEZ2so1+15wAYhuF114Z1AldBipSzSVBbecUOT7IqXufKNW+OcvHLMkoPGhmcS65ovRI6maac4VfAsCwdx+NI7BOFo6RfTWOsYzdY3NiZ+QUrbxEmi5IKdVmw/gEcl1tmDW6kwBg3ExD//chMuOVQKgDI0xFXoG4D8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786992089; c=relaxed/simple; bh=brncUiGnalGElaj9h67hLSOtPMjkT92NThj25A70XkU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G+h/cpN3xuvWxIKA6NNCxZPe7O/JXLzkPzLU8JfSwyoldP8+A1J27qdCs+F0us13ddvU2YKBZUMub3QXH3DzfVrMoJTTR/XPLXF0TI9kg+clPog2724pCNXrFnA++0Dhgexdx5hxKQUEdZED5AUwgx1syf9axxvGQ/W6Y6KUS3w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y1Vz6gaR; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y1Vz6gaR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1786992088; x=1818528088; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=brncUiGnalGElaj9h67hLSOtPMjkT92NThj25A70XkU=; b=Y1Vz6gaRQOLR9J9LraYBRF9AqGpCqWgLA8YNP4Wrw8iKSdnnaKcrLxQR bXjfhRH3dlZ086Yc1nzmF3U+R7LlvRt0pt4snb8rNkz3EGvl1Ei7rWiao W57U0YLHkJatGkYcYHLWmlFJbkd9pU8y54wxwMuEwixZTyNmGObZPdha/ jKIHsixP9d6TNOrqf/pnJM1OQ6e1zaoF96Lbi341zSWe4BZsV6OT20N4m 9YtJKg0p5cJqoVR2oe2jKohdztr0wCURuivcyGAjDTXE9YC1+tqOg1kvX Z/anldPC04sVSskCsCLDt/2U61Xy1md1/rA1jnV2T4akJVH2jdKI+GlIB w==; X-CSE-ConnectionGUID: Pda1ncQSRd218QZCNiiTeA== X-CSE-MsgGUID: WQWfelcER/iOypK4hILqGA== X-IronPort-AV: E=McAfee;i="6800,10657,11878"; a="98066081" X-IronPort-AV: E=Sophos;i="6.25,229,1779174000"; d="scan'208";a="98066081" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2026 11:41:25 -0700 X-CSE-ConnectionGUID: IA6c4iE8QVKk2lCkifwxcA== X-CSE-MsgGUID: 4SCalm5ESNupnBi2QEH7Pg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,229,1779174000"; d="scan'208";a="263656963" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2026 11:41:24 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , linux-kernel@vger.kernel.org, Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Subject: [PATCH v8 3/8] KVM: x86/pmu: Rename and move vcpu_get_perf_capabilities() to pmu.h Date: Mon, 17 Aug 2026 11:31:37 -0700 Message-ID: <20260817183143.226156-4-zide.chen@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260817183143.226156-1-zide.chen@intel.com> References: <20260817183143.226156-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This is in preparation for it to be called from common x86 code, for example kvm_need_rdpmc_intercept(), to check the guest's PERF_METRICS capability. Rename it to kvm_vcpu_get_perf_caps() to indicate that it's part of the common API, and shorten _capabilities to _caps. No functional change intended. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi Reviewed-by: Jim Mattson --- v8: - remove include "cpuid.h" from pmu_intel.h. v5: new patch. --- arch/x86/kvm/pmu.h | 8 ++++++++ arch/x86/kvm/vmx/pmu_intel.c | 6 +++--- arch/x86/kvm/vmx/pmu_intel.h | 12 +----------- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 090c9bbb74f4..82f955e5a450 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -271,6 +271,14 @@ static inline bool kvm_pmu_is_fastpath_emulation_allowed(struct kvm_vcpu *vcpu) X86_PMC_IDX_MAX); } +static inline u64 kvm_vcpu_get_perf_caps(struct kvm_vcpu *vcpu) +{ + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) + return 0; + + return vcpu->arch.perf_capabilities; +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); int kvm_pmu_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index df51a17b6e17..100c072b7fb3 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -190,13 +190,13 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); case MSR_IA32_PEBS_ENABLE: - ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; + ret = kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_PEBS_FORMAT; break; case MSR_IA32_DS_AREA: ret = guest_cpu_cap_has(vcpu, X86_FEATURE_DS); break; case MSR_PEBS_DATA_CFG: - perf_capabilities = vcpu_get_perf_capabilities(vcpu); + perf_capabilities = kvm_vcpu_get_perf_caps(vcpu); ret = (perf_capabilities & PERF_CAP_PEBS_BASELINE) && ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3); break; @@ -551,7 +551,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); } - perf_capabilities = vcpu_get_perf_capabilities(vcpu); + perf_capabilities = kvm_vcpu_get_perf_caps(vcpu); if (intel_pmu_lbr_is_compatible(vcpu) && (perf_capabilities & PERF_CAP_LBR_FMT)) memcpy(&lbr_desc->records, &vmx_lbr_caps, sizeof(vmx_lbr_caps)); diff --git a/arch/x86/kvm/vmx/pmu_intel.h b/arch/x86/kvm/vmx/pmu_intel.h index 5d9357640aa1..dd447d8b6fdd 100644 --- a/arch/x86/kvm/vmx/pmu_intel.h +++ b/arch/x86/kvm/vmx/pmu_intel.h @@ -4,19 +4,9 @@ #include -#include "cpuid.h" - -static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu) -{ - if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) - return 0; - - return vcpu->arch.perf_capabilities; -} - static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu) { - return (vcpu_get_perf_capabilities(vcpu) & PERF_CAP_FW_WRITES) != 0; + return (kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_FW_WRITES) != 0; } bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu); -- 2.55.0