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Tue, 18 Aug 2026 01:09:15 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.vger.kernel.org, Sreeshankar K Subject: [PATCH 06/12] clk: qcom: rpmh: Add SM7250 rpmh clocks Date: Tue, 18 Aug 2026 08:07:48 +0000 Message-ID: <20260818080754.4362-7-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260818080754.4362-1-sreeshankar0910@gmail.com> References: <20260818080754.4362-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the RPMH clocks present in SM7250 SoC. Signed-off-by: Sreeshankar K --- drivers/clk/qcom/clk-rpmh.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 6367b2a5a..f4cafa274 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -1011,6 +1011,29 @@ static const struct clk_rpmh_desc clk_rpmh_hawi = { .num_clks = ARRAY_SIZE(hawi_rpmh_clocks), }; +static struct clk_hw *sm7250_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_d.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_d_ao.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm7250 = { + .clks = sm7250_rpmh_clocks, + .num_clks = ARRAY_SIZE(sm7250_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -1120,6 +1143,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75}, { .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450}, { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, + { .compatible = "qcom,sm7250-rpmh-clk", .data = &clk_rpmh_sm7250}, { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, -- 2.43.0