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[2001:4c4e:1b92:9600:62a3:1d8d:dd4e:a0dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b1441748sm4935688f8f.8.2026.08.19.03.03.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2026 03:03:20 -0700 (PDT) From: Igor Paunovic To: support Cc: Igor Paunovic , Sandy Huang , Heiko Stuebner , Andy Yan , Cristian Ciocaltea , Sebastian Reichel , Chaoyi Chen , Alexey Charkov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel , linux-rockchip , linux-arm-kernel , linux-kernel Subject: Re: [PATCH v2] drm/rockchip: vop2: Scale the AXI clock to the bandwidth the mode needs Date: Wed, 19 Aug 2026 12:02:47 +0200 Message-ID: <20260819100249.7945-1-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026081916331211222713@armdesigner.com> References: <20260813154501.21332-1-royalnet026@gmail.com> <2026081916331211222713@armdesigner.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Owen, Thank you - and thank you for bringing this to the list. A fanless RK3588J chassis at 60C ambient running dual HDMI plus DP is a far stronger argument for scaling this clock than my bench ever was, and the +3-5C junction delta at 750 MHz is exactly the number the power/thermal side of this discussion was missing. On your question - both, sequenced, because they answer different questions: - The BSP 6.1 48h soak first. That is your production reality and it needs no bring-up; what it buys is the real-world deployment evidence, and with your permission I will cite it in the v3 cover letter alongside the multi-CRTC tearing observation. - The mainline clean-room run when your DTS bring-up is ready. v3 will be against drm-misc-next, and that run is the one I would attach your Tested-by to, so the tag attests the tree the patch actually targets. No rush on this one - if it lands during the v3 review cycle rather than before it, that is still perfect timing. I will CC you on v3. It will state the FRL/ACLK relationship explicitly (on my board the HDMI FRL path holds the clock at 750 MHz independently, which is why the DP path was the one that exposed the scaling gap), and it will pick one direction for commit_setup vs commit_tail and defend it in the cover letter - the question to the maintainers about a rockchip-wide hook pair is still open, and v3 cannot wait on it forever. Regards, Igor