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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF00002318.mail.protection.outlook.com (10.167.242.228) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.339.3 via Frontend Transport; Thu, 20 Aug 2026 09:10:37 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Thu, 20 Aug 2026 04:10:37 -0500 Received: from xhddevverma40x.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.45 via Frontend Transport; Thu, 20 Aug 2026 04:10:34 -0500 From: Devendra K Verma To: , , , CC: , , , , Subject: [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC Date: Thu, 20 Aug 2026 14:40:24 +0530 Message-ID: <20260820091025.683506-2-devverma@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091025.683506-1-devverma@amd.com> References: <20260820091025.683506-1-devverma@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|IA4PR12MB9834:EE_ X-MS-Office365-Filtering-Correlation-Id: e2c4a85d-f015-4025-06d0-08defe9ae694 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|1800799024|23010399003|11063799006|18002099003|22082099003|10067099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: teWAX8KKVgihcyg80OmaAigZAHokImRiZEaIwcpAlPRJxv2el8xZi8yztAVb0YRDbgVMCPCMf9cNcQNykYsh3JK/SM0TKBS8FQ2bRQV6U76jXjjfd2g77kyQ5u9JqLRPJVSVwXnTJ4yXiB2l5qu3dK+wCumPxSbwQCWjNyl1Z15SL2yk3o/JYGvzWwkfn7sDQ/hee9E65uiFoPAYzCCnsA9zd1xFYBgwd/pggfIdf+lvfNp3dsL3wc+kRIgsc1aSCTJGLr+K+bKCmOrE1CL9zIJ9xZSNEj8S6RjYfN79q4MysSAIKO9wKei7hgkNzbGbe/CZeBxUwoIV4tRhHig9dobvmVu93OuNW0V0pgE7sN8q774BoEVnjadHiP2X2c8lgBaes0dDMjnr6btCO7wkZ+HaJu0xXn0/bL+KWkqcOTWDfjuqweVy5dsV5+WRttgx X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Aug 2026 09:10:37.8821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2c4a85d-f015-4025-06d0-08defe9ae694 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR12MB9834 As per, 'Designware Cores PCI Express DM Controller - Reference Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports the channel separation mechanisms. Basically, the HDMA IP allows the user to configure the separation between DMA channel registers and retrieve it via the VSEC capability mentioned above. HDMA IP supports the channel register space separation from 256B to 32KB. Default supported size is 256B. Signed-off-by: Devendra K Verma Reviewed-by: Frank Li --- Changes in v4: o No change Changes in v3: o Reverted the trivial changes / typos. Changes in v2: o Replaced 'ch_sep_sz' with 'ch_space_sz' wherever applicable upon reviewer recommendation. o Dropped 1/3 patch of this series, after review, now the 2/3 is 1/2 of the current patch series. Changes in v1: o Modified dw_edma_get_ch_sep_sz() as per review comment. The function now supports ch_sep_sz up to 32KB. o Updated to description to reflect the supported channel separation sizes. --- drivers/dma/dw-edma/dw-edma-pcie.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 791c46e8ae4c..f287879b2cb9 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -33,6 +33,8 @@ #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 #define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) +/* AMD CPM6 (Xilinx) supported cap */ +#define DW_PCIE_XILINX_CPM6_VSEC_CH_SEP GENMASK(18, 16) #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) @@ -73,6 +75,7 @@ struct dw_edma_pcie_data { u16 wr_ch_cnt; u16 rd_ch_cnt; u64 devmem_phys_off; + u32 ch_space_sz; }; static const struct dw_edma_pcie_data snps_edda_data = { @@ -189,6 +192,13 @@ static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) return pci_irq_vector(to_pci_dev(dev), nr); } +static u32 dw_edma_get_ch_space_sz(u32 val) +{ + if (val > 0 && val <= 7) + return 256 << val; + return 256; +} + static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) { struct pci_dev *pdev = to_pci_dev(dev); @@ -279,6 +289,10 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, pdata->mf = map; pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); + if (pdev->device == PCI_DEVICE_ID_XILINX_B00F) + pdata->ch_space_sz = dw_edma_get_ch_space_sz + (FIELD_GET(DW_PCIE_XILINX_CPM6_VSEC_CH_SEP, val)); + pci_read_config_dword(pdev, vsec + 0xc, &val); pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); -- 2.43.0