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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499aa0fd7a9sm165259515e9.2.2026.08.20.02.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:21:51 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH 3/3] ARM: dts: stm32: add missed arm,num-irq-priority-bits for stm32h743 Date: Thu, 20 Aug 2026 11:21:38 +0200 Message-ID: <20260820092143.44829-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820092143.44829-1-dario.binacchi@amarulasolutions.com> References: <20260820092143.44829-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add missed arm,num-irq-priority-bits to fix below CHECK_DTBS warning: arch/arm/boot/dts/st/stm32h747i-disco.dtb: interrupt-controller@e000e100 (arm,armv7m-nvic): 'arm,num-irq-priority-bits' is a required property from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/st/stm32h743.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi index 2f19cfbc57ad..845d13c61da8 100644 --- a/arch/arm/boot/dts/st/stm32h743.dtsi +++ b/arch/arm/boot/dts/st/stm32h743.dtsi @@ -732,6 +732,10 @@ gpiok: gpio@58022800 { }; }; +&nvic { + arm,num-irq-priority-bits = <4>; +}; + &systick { clock-frequency = <250000000>; status = "okay"; --- base-commit: a4ff2be345d0abc943da8dd8da98151843b750dc branch: stm32-nvic-irq-priority-bits -- 2.43.0