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From: Jiaxing Hu <gahing@gahingwoo.com>
To: royalnet026@gmail.com
Cc: tomeu@tomeuvizoso.net, heiko@sntech.de,
	chaoyi.chen@rock-chips.com, alchark@flipper.net,
	dri-devel@lists.freedesktop.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support
Date: Thu, 20 Aug 2026 22:07:15 +1200	[thread overview]
Message-ID: <20260820100715.750660-1-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260819184838.6723-1-royalnet026@gmail.com>

Hi Igor, and the list,

The single field sweep I owed, and said on the 19th was late. It is run.

Each of the five fields where my 0x4050 differs from upstream's 0x124 was moved
to upstream's value on its own, with the other four left alone. Two shapes, a
5x5 convolution at 128 output channels and a pointwise at 88, three baselines
across the log with no drift between them.

  field, mine to upstream    output                    completion
  RGP_CNTER   8 to 0         wrong, 0 of 128 and       no hang
                             14 of 88, maxdiff 255
  RESERVED_0  34 to 0        matches the baseline      times out
  SIZE_E_1    0 to 1         matches the baseline      no hang
  SIZE_E_0    4 to 1         wrong                     times out
  OW_SRC      1 to 0         wrong                     times out
  upstream's whole 0x124     wrong                     times out

So four of the five are load bearing on RK3576, and they fail in three different
ways. RGP_CNTER is purely arithmetic, it computes the wrong answer and finishes.
RESERVED_0 is purely a completion field, the output is identical to the baseline
on both shapes and the job still hangs. SIZE_E_0 and OW_SRC do both.

Two things to read carefully rather than take at face value. RESERVED_0's score
prints after its timeout, so the hang is the result there and the number beside
it is colour. And every timeout landed inside the entry that set the value, with
a health check passing after each, so none of it is a hang leaking from the
entry before.

SIZE_E_1 is the one that does nothing. I have left it at 0 rather than moving it
to upstream's 1, because two shapes is not every shape, and written into the
comment that it was measured not to matter. If you would rather I match upstream
there and shrink the diff by a field, say so and I will.

The merge request now carries this table in the comment above the register.

  https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/43804

And something I should have said two mails ago. Thank you for the v8 Tested-by
on 1/12 and 2/12. A differential base on the same machine in the same session
was more than I asked for, and the row that matters is the one where the two
kernels agree, 12 and 8 induced resets against 12 and 13, all clean, 48 of 48
both passes on either. I have written to you twice since without acknowledging
it, which was careless.

Where it lands, and I would rather be exact than generous to myself. 1/13 is
unchanged in v9 and your tag carries. 2/13 is not the patch you tested, since it
folds in the interrupt mask you raised, so I have left your tag off it. When v9
posts I will say so on the thread rather than quietly carry it across.

Have a good trip.

Regards,
Jiaxing

  parent reply	other threads:[~2026-08-20  7:15 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-12  9:40 [PATCH v7 00/10] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-12  9:40 ` [PATCH v7 01/10] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-12 12:47   ` Igor Paunovic
2026-08-12  9:40 ` [PATCH v7 02/10] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-13  7:04   ` Krzysztof Kozlowski
2026-08-12  9:40 ` [PATCH v7 03/10] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-08-13  7:06   ` Krzysztof Kozlowski
2026-08-14  8:21     ` Jiaxing Hu
2026-08-12  9:40 ` [PATCH v7 04/10] dt-bindings: iommu: rockchip: allow the RK3576 NPU MMU clock set Jiaxing Hu
2026-08-12 10:45   ` Diederik de Haas
2026-08-13  9:27     ` Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 05/10] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 06/10] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 07/10] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-12 12:48   ` Igor Paunovic
2026-08-13  9:26     ` Jiaxing Hu
2026-08-13  9:56       ` Igor Paunovic
2026-08-14  8:26         ` Jiaxing Hu
2026-08-14 11:08           ` Igor Paunovic
     [not found]   ` <20260814110841.11238-1-royalnet026@gmail.com>
2026-08-15  3:12     ` Jiaxing Hu
2026-08-15 13:05       ` Igor Paunovic
2026-08-16  4:12         ` Jiaxing Hu
2026-08-16 18:53           ` Igor Paunovic
2026-08-16 19:58             ` Jiaxing Hu
2026-08-16 20:25               ` Igor Paunovic
2026-08-17  8:31                 ` Jiaxing Hu
2026-08-17  9:45                 ` Jiaxing Hu
2026-08-17 10:00                   ` Igor Paunovic
2026-08-17 10:20                     ` Jiaxing Hu
2026-08-17 11:05                       ` Igor Paunovic
2026-08-19 10:57                 ` Jiaxing Hu
2026-08-19 15:46                   ` Igor Paunovic
2026-08-19 18:48                     ` Igor Paunovic
2026-08-19 21:50                       ` Jiaxing Hu
2026-08-20 10:07                       ` Jiaxing Hu [this message]
2026-08-20 18:50                         ` Igor Paunovic
2026-08-12  9:41 ` [PATCH v7 09/10] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 10/10] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu
2026-08-12 10:20   ` Chaoyi Chen

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