From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29F5D3C3F42 for ; Thu, 20 Aug 2026 16:20:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787242841; cv=none; b=cYXhQJ7NgGfPrY6GLFHeAuvfYqKgKFSjNqk/baCbb29XZW0LnpPMu7tV9r21XfriE4NUw6tWqPm08sCMDS66O9uVgSNj/J9MymfIBeplLeqRhH21H0y7n+brr6YQyBtXoDNpwrrjfKheLViFav7bF8zEjTimieaCDu8IqTjF0wE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787242841; c=relaxed/simple; bh=2KWEc1Be1xcgWQaOrW1Ohh9UqTjT7O1hSeHYQAeEGZY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=u+Mp1KzWifg6x4DYJZJkURSvNygvSyQrP/EK9gxUc65FiVkc6ZYdexgmgpye4+/UDO4AUu9LZITKSUJJaVza/Z7W0JkzynedY3C7eOTKL41yBjG3CyPW6iknaZQedBGYwXEsdWLTLkV7yatdGxftm5QVcjVgNvZXEC9g6+3br3o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=kcgEhinB; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="kcgEhinB" Received: from mail01.layka.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id EE2388833F; Thu, 20 Aug 2026 18:20:35 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id VhwsC8wBm8D7; Thu, 20 Aug 2026 18:20:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1787242835; bh=2KWEc1Be1xcgWQaOrW1Ohh9UqTjT7O1hSeHYQAeEGZY=; h=From:To:Cc:Subject:Date; b=kcgEhinBIwJUt4s6CHDIJpmljXtd48Vst2w520RrCk9nICMS32NTWeKNwrczKMFxn fwZdl/QxJ00YlOelrF4ph3fpxIaXJ7CCxudYcBlao8P6+z+FOfEW4/tnpi03jT+jz0 BDMxHS0Ls+CzQuvP9KYcUgan5CxBvMZoQd0o0vhk41AvR6G1tmYIGrt4Ir9vaEveDx TI3HRb8ukjxsZYGx4+Iw+GHJG8K9H3UED1H6ylAafJiqtU528Zok/hVYqkxYbCXKGW OSNyfRhbhIA33yGwr0lg1nP8wOq6s8ydQmwNS/s2iatjxEEBm0lcbtt7n50Sj+4TF6 EKev38k7Mgzyw== From: Rustam Adilov To: Thomas Gleixner , Birger Koblitz , Bert Vermeulen , John Crispin , linux-kernel@vger.kernel.org Cc: Rustam Adilov , Carlo Szelinsky Subject: [PATCH v3] irqchip/irq-realtek-rtl: change to readl_be and writel_be Date: Thu, 20 Aug 2026 21:20:17 +0500 Message-ID: <20260820162017.28507-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When CONFIG_SWAP_IO_SPACE is enabled, readl() is changed to perform a swap from little endian device to big endian CPU and vice versa for writel(). This is incorrect because the Realtek Interrupt controller is a big endian device and so the LE to BE conversions are unwanted. Fix this by converting the MMIO accesses to readl_be() and writel_be(). Tested-by: Carlo Szelinsky Signed-off-by: Rustam Adilov --- Changes in v3: - Make the commit message more sensible, hopefully. - Change the __raw variants to readl_be and writel_be. - Add the note in the driver that the controller is big endian. Changes in v2: - Make the commit message clearer. drivers/irqchip/irq-realtek-rtl.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realtek-rtl.c index c8becb458da2..26e52c3f8c68 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -1,5 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Realtek Interrupt controller. + * + * The Realtek Interrupt controller is a big endian device found in the + * Realtek MIPS SoCs. + * * Copyright (C) 2020 Birger Koblitz * Copyright (C) 2020 Bert Vermeulen * Copyright (C) 2020 John Crispin @@ -50,18 +55,18 @@ static inline void enable_gimr(unsigned int cpu, unsigned int hw_irq) { u32 gimr; - gimr = readl(REG(cpu, RTL_ICTL_GIMR)); + gimr = readl_be(REG(cpu, RTL_ICTL_GIMR)); gimr |= BIT(hw_irq); - writel(gimr, REG(cpu, RTL_ICTL_GIMR)); + writel_be(gimr, REG(cpu, RTL_ICTL_GIMR)); } static inline void disable_gimr(unsigned int cpu, unsigned int hw_irq) { u32 gimr; - gimr = readl(REG(cpu, RTL_ICTL_GIMR)); + gimr = readl_be(REG(cpu, RTL_ICTL_GIMR)); gimr &= ~BIT(hw_irq); - writel(gimr, REG(cpu, RTL_ICTL_GIMR)); + writel_be(gimr, REG(cpu, RTL_ICTL_GIMR)); } static void write_irr(unsigned int cpu, int hw_irq, u32 value) @@ -71,9 +76,9 @@ static void write_irr(unsigned int cpu, int hw_irq, u32 value) unsigned int shift = IRR_SHIFT(hw_irq); u32 irr; - irr = readl(irr0 + offset) & ~(0xf << shift); + irr = readl_be(irr0 + offset) & ~(0xf << shift); irr |= (value & 0xf) << shift; - writel(irr, irr0 + offset); + writel_be(irr, irr0 + offset); } static void realtek_ictl_unmask_irq(struct irq_data *i) @@ -159,7 +164,8 @@ static void realtek_irq_dispatch(struct irq_desc *desc) unsigned int hw_irq; chained_irq_enter(chip, desc); - pending = readl(REG(cpu, RTL_ICTL_GIMR)) & readl(REG(cpu, RTL_ICTL_GISR)) & output->mask; + pending = readl_be(REG(cpu, RTL_ICTL_GIMR)) & + readl_be(REG(cpu, RTL_ICTL_GISR)) & output->mask; if (unlikely(!pending)) { spurious_interrupt(); -- 2.55.0