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Sat, 22 Aug 2026 08:08:07 -0700 (PDT) From: Felix Gu Date: Sat, 22 Aug 2026 23:07:47 +0800 Subject: [PATCH 1/3] PCI: dra7xx: Fix clock enable leak on probe failure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260822-dra7xx-v1-1-23e204d5548b@gmail.com> References: <20260822-dra7xx-v1-0-23e204d5548b@gmail.com> In-Reply-To: <20260822-dra7xx-v1-0-23e204d5548b@gmail.com> To: Vignesh Raghavendra , Siddharth Vadapalli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , Luca Ceresoli , Sekhar Nori Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Felix Gu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787411275; l=1209; i=ustc.gu@gmail.com; h=from:subject:message-id; bh=iqwaq39/Zpa0iH6/a6W3yQV4x79xW81LRfZe/TmtbhQ=; b=JQwJxBp9JSiXLkuvgP9DsAqIhnNVN95oebkqBf5QP+o8m9TooJuuD3/GmQ47Qgmh0RJ1HbYN/ XhZFZF9+3GCASDzQMKX+JxGYZMzSbVHilzqclpMzDdh1CfPZODqjapy X-Developer-Key: i=ustc.gu@gmail.com; a=ed25519; pk=fjUXwmjchVN7Ja6KGP55IXOzFeCl9edaHoQIEUA+/hw= dra7xx_pcie_probe() enables the optional clock but never disables it when probing fails afterwards. Switch to devm_clk_get_optional_enabled(), which disables the clock automatically on failure. Fixes: 5af9405397bf ("PCI: dra7xx: Get an optional clock") Signed-off-by: Felix Gu --- drivers/pci/controller/dwc/pci-dra7xx.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 6ae5b27e27b3..d43253f7dea6 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -732,15 +732,11 @@ static int dra7xx_pcie_probe(struct platform_device *pdev) if (!link) return -ENOMEM; - dra7xx->clk = devm_clk_get_optional(dev, NULL); + dra7xx->clk = devm_clk_get_optional_enabled(dev, NULL); if (IS_ERR(dra7xx->clk)) return dev_err_probe(dev, PTR_ERR(dra7xx->clk), "clock request failed"); - ret = clk_prepare_enable(dra7xx->clk); - if (ret) - return ret; - for (i = 0; i < phy_count; i++) { snprintf(name, sizeof(name), "pcie-phy%d", i); phy[i] = devm_phy_get(dev, name); -- 2.43.0