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Sun, 23 Aug 2026 22:35:12 -0700 (PDT) X-Received: by 2002:a17:90b:3d85:b0:392:c80b:8eff with SMTP id 98e67ed59e1d1-395c3573af2mr41879275a91.11.1787549711613; Sun, 23 Aug 2026 22:35:11 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327ff728ca7sm20166492eec.3.2026.08.23.22.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Aug 2026 22:35:11 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Mon, 24 Aug 2026 11:04:59 +0530 Subject: [PATCH v3 1/2] PCI: dwc: Force L2 link entry on shutdown/reboot without D3cold check Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260824-shutdown-v3-1-81c14bb7a1af@oss.qualcomm.com> References: <20260824-shutdown-v3-0-81c14bb7a1af@oss.qualcomm.com> In-Reply-To: <20260824-shutdown-v3-0-81c14bb7a1af@oss.qualcomm.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Krishna Chaitanya Chundru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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If no endpoint supports it, the function returns early and leaves the link up. Querying D3cold support during shutdown is actively harmful, not just slow: pci_host_common_d3cold_possible() requires every active endpoint to already be in PCI_D3hot, and returns false otherwise. If any endpoint is still in D0 -- which is common, since endpoint drivers aren't guaranteed to have suspended by the time the host's shutdown path runs the check fails and dw_pcie_suspend_noirq() returns early without ever moving the link to L2, leaving it up right up to the point where the system cuts power/clocks to the controller. Detect the shutdown/reboot case via system_state and skip straight to forcing the link into L2, the same sequence used for the D3cold-capable case. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 06722259d2e3..98cd9dd2c7d7 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -1222,16 +1223,29 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) int dw_pcie_suspend_noirq(struct dw_pcie *pci) { - bool pme_capable = false; + bool shutdown = system_state == SYSTEM_HALT || + system_state == SYSTEM_POWER_OFF || + system_state == SYSTEM_RESTART; + bool d3cold, pme_capable = false; int ret = 0; u32 val; if (!dw_pcie_link_up(pci)) goto stop_link; - if (!pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable)) + /* + * During reboot/halt/poweroff the link is going away regardless, so + * force L2 entry without checking whether endpoints have transitioned + * to D3hot -- there's no point walking the bus to find out. + */ + if (shutdown) + goto d3cold; + + d3cold = pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable); + if (!d3cold) return 0; +d3cold: if (pci->pp.ops->pme_turn_off) { pci->pp.ops->pme_turn_off(&pci->pp); } else { -- 2.34.1