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Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple lane configurations using four PHY segments (A/B/C/D). The active topology is selected by firmware through a TCSR configuration register and may be configured as x16, x8+x8, x8+x4+x4, or x8+x4+x2+x2. The binding describes the register regions, clocks, resets, power domains, regulators, PHY provider interface, clock provider interface, and the qcom,link-mode property used by the driver to discover the active lane configuration programmed by firmware. Signed-off-by: Krishna Chaitanya Chundru --- .../bindings/phy/qcom,nord-qmp-pcie-phy.yaml | 276 +++++++++++++++++++++ 1 file changed, 276 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml new file mode 100644 index 000000000000..3575e99dadfd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Nord QMP Bifurcated PCIe PHY + +maintainers: + - Krishna Chaitanya Chundru + +description: | + The Qualcomm Nord PCIe PHY is a Gen5-capable QMP PCIe PHY composed + of four PHY ports (A/B/C/D). The ports can be combined to support + multiple lane topologies, including x16, x8+x8, x8+x4+x4 and + x8+x4+x2+x2 configurations. + + The selected topology is determined by the PCIe link configuration mode + programmed in TCSR registers. Depending on the selected mode, PHY ports + may operate independently or be grouped together to form wider PCIe links. + + Each port provides dedicated register space, clocks, resets and power + resources required for PHY operation. + +properties: + compatible: + enum: + - qcom,nord-qmp-gen5x16-pcie-phy + + reg: + minItems: 4 + maxItems: 4 + + reg-names: + items: + - const: port_a + - const: port_b + - const: port_c + - const: port_d + + clocks: + minItems: 17 + maxItems: 17 + + clock-names: + items: + - const: aux_a + - const: cfg_ahb_a + - const: rchng_a + - const: pipe_a + - const: aux_b + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: aux_c + - const: cfg_ahb_c + - const: rchng_c + - const: pipe_c + - const: aux_d + - const: cfg_ahb_d + - const: rchng_d + - const: pipe_d + - const: ref + + power-domains: + minItems: 4 + maxItems: 4 + + power-domain-names: + items: + - const: port_a + - const: port_b + - const: port_c + - const: port_d + + resets: + minItems: 8 + maxItems: 8 + + reset-names: + items: + - const: port_a + - const: port_a_nocsr + - const: port_b + - const: port_b_nocsr + - const: port_c + - const: port_c_nocsr + - const: port_d + - const: port_d_nocsr + + vdda-phy-a-supply: true + + vdda-phy-b-supply: true + + vdda-phy-c-supply: true + + vdda-phy-d-supply: true + + vdda-pll-a-supply: true + + vdda-pll-b-supply: true + + vdda-pll-c-supply: true + + vdda-pll-d-supply: true + + qcom,link-mode: + description: | + Reference to the TCSR syscon and the offset of the + TCSR_PCIE_LINK_CONFIG_MODE register. + 0 (QMP_PCIE_NORD_MODE_X16) — all ports ganged as x16 + 1 (QMP_PCIE_NORD_MODE_X8_X8) — x8 (port A) + x8 (port B+C+D) + 2 (QMP_PCIE_NORD_MODE_X8_X4_X4) — x8 (A) + x4 (B) + x4 (C+D) + 3 (QMP_PCIE_NORD_MODE_X8_X4_X2_X2)— x8 (A) + x4 (B) + x2 (C) + x2 (D) + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle of the TCSR syscon + - description: Offset of TCSR_PCIE_LINK_CONFIG_MODE register + + "#clock-cells": + const: 1 + description: | + Selects the pipe clock output by port index (0=A, 1=B, 2=C, 3=D). + GCC pipe-clock mux parents reference this provider. + + clock-output-names: + minItems: 1 + maxItems: 4 + description: Names for each port pipe clock output. + + "#phy-cells": + const: 1 + description: | + Selects the PHY instance by index: + 0 — port A (up to Gen4 x8; anchor in x16 mode) + 1 — port B (up to Gen4 x4) + 2 — port C (up to Gen2 x2) + 3 — port D (up to Gen2 x2) + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - vdda-phy-a-supply + - vdda-phy-b-supply + - vdda-phy-c-supply + - vdda-phy-d-supply + - vdda-pll-a-supply + - vdda-pll-b-supply + - vdda-pll-c-supply + - vdda-pll-d-supply + - qcom,link-mode + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@1b00000 { + compatible = "qcom,nord-qmp-gen5x16-pcie-phy"; + + reg = <0x0 0x01b00000 0x0 0x10000>, + <0x0 0x01b10000 0x0 0x10000>, + <0x0 0x01b20000 0x0 0x10000>, + <0x0 0x01b30000 0x0 0x10000>; + reg-names = "port_a", + "port_b", + "port_c", + "port_d"; + + clocks = <&gcc GCC_PCIE_A_PHY_AUX_CLK>, + <&gcc GCC_PCIE_A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_A_PIPE_CLK>, + <&gcc GCC_PCIE_B_PHY_AUX_CLK>, + <&gcc GCC_PCIE_B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_B_PIPE_CLK>, + <&gcc GCC_PCIE_C_PHY_AUX_CLK>, + <&gcc GCC_PCIE_C_CFG_AHB_CLK>, + <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_C_PIPE_CLK>, + <&gcc GCC_PCIE_D_PHY_AUX_CLK>, + <&gcc GCC_PCIE_D_CFG_AHB_CLK>, + <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_D_PIPE_CLK>, + <&tcsrcc TCSR_PCIE_CLKREF_EN>; + clock-names = "aux_a", + "cfg_ahb_a", + "rchng_a", + "pipe_a", + "aux_b", + "cfg_ahb_b", + "rchng_b", + "pipe_b", + "aux_c", + "cfg_ahb_c", + "rchng_c", + "pipe_c", + "aux_d", + "cfg_ahb_d", + "rchng_d", + "pipe_d", + "ref"; + + assigned-clocks = <&gcc GCC_PCIE_A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_C_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_D_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>, <100000000>, + <100000000>, <100000000>; + + power-domains = <&gcc GCC_PCIE_A_PHY_GDSC>, + <&gcc GCC_PCIE_B_PHY_GDSC>, + <&gcc GCC_PCIE_C_PHY_GDSC>, + <&gcc GCC_PCIE_D_PHY_GDSC>; + power-domain-names = "port_a", + "port_b", + "port_c", + "port_d"; + + resets = <&gcc GCC_PCIE_A_PHY_COM_BCR>, + <&gcc GCC_PCIE_A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_B_PHY_COM_BCR>, + <&gcc GCC_PCIE_B_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_C_PHY_COM_BCR>, + <&gcc GCC_PCIE_C_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_D_PHY_COM_BCR>, + <&gcc GCC_PCIE_D_NOCSR_COM_PHY_BCR>; + reset-names = "port_a", + "port_a_nocsr", + "port_b", + "port_b_nocsr", + "port_c", + "port_c_nocsr", + "port_d", + "port_d_nocsr"; + + vdda-phy-a-supply = <&vreg_l6a_1p2>; + vdda-phy-b-supply = <&vreg_l4a_1p2>; + vdda-phy-c-supply = <&vreg_l4a_1p2>; + vdda-phy-d-supply = <&vreg_l4a_1p2>; + vdda-pll-a-supply = <&vreg_l1e_0p9>; + vdda-pll-b-supply = <&vreg_l1e_0p9>; + vdda-pll-c-supply = <&vreg_l1e_0p9>; + vdda-pll-d-supply = <&vreg_l1e_0p9>; + + qcom,link-mode = <&tcsr 0x71050>; + + #clock-cells = <1>; + clock-output-names = "pcie_a_pipe_clk", + "pcie_b_pipe_clk", + "pcie_c_pipe_clk", + "pcie_d_pipe_clk"; + + #phy-cells = <1>; + status = "disabled"; + }; + }; -- 2.34.1