From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20128330B0E for ; Tue, 25 Aug 2026 03:05:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787627139; cv=none; b=DT2juek2m0tCNKOAvYMSfCKyAyHaDk3ts6lMMsnZ6RWw9VFQLElIAjXoL/Jn89i8NH1JcuScYJxicURjr2NyiCvfi3lpS6UTUkkepfW8GtmjJkAhedFC5kNxRlxKn/Y+NtWITc61iU8ly2k6zQ4Bbpre4vLc22vTpaOFuVpIpt0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787627139; c=relaxed/simple; bh=obY+i0zT3kRzbcG35TnXj+vhLQGxMu/UqFxZqhZ1R6A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XyZLY0ARoGvJnbWptLOWDs+aSqbSIDNXVvbHuW61d1YzlIbgzyNM3zrJ9AyX9wPaO6ftjo4gQB0emsJiMVzEWB4btLAucat/UlXZdR5W7imwCNDMSpbCDo0zorag65GDF8ng4Ip1AP2FFMmIR7pIIsrOBQ2ZGeUv9sPQcfgWc3o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=jdFDvFb2; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="jdFDvFb2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=Kx Z9cgvNltAK9q7EPBGQ4dIFVYNFcy9EDy4BATigJec=; b=jdFDvFb20LM1C+Nx/d wL9xFWcmxjei/bYs+qf/zlOEwjfT77s3e4iSGMJlH1q2epmm8eGEfbvywYoJu3t7 GdT94UCpl0k5JE660YTzln88cp+9NH4+8Ge2/wMagQqSohA7yqQMn25jqbYdcGse eYHf+bG1LfqZQS8BQX/VhJIGc= Received: from DESKTOP-93MEKVV.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDn7wZVBo1qi9LKOw--.36731S2; Tue, 25 Aug 2026 11:04:54 +0800 (CST) From: Li Dou To: maz@kernel.org Cc: li8d6kernel@163.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, radu@rendec.net, tglx@kernel.org Subject: Re: [PATCH] irqchip/gic-v3: Remove the ISB between AP0Rn and AP1Rn Date: Tue, 25 Aug 2026 11:04:54 +0800 Message-ID: <20260825030454.1280-1-li8d6kernel@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <87bjaro4th.wl-maz@kernel.org> References: <87bjaro4th.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:PigvCgDn7wZVBo1qi9LKOw--.36731S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cr4UXw4UuFW3Aw1xKw1xXwb_yoW8Xry3pw 4aka4DZFs8C3ZxGw4SqF12vF18u393Wr4UXFn8Gr18KF95ZFWkGry09F4Y9ryqyrs2yw1Y q3yjya95Ga4FyFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUPMaUUUUUU= X-CM-SenderInfo: dolyvlxnhu0vro6rljoofrz/xtbC9xaUDWqNBlbvnAAA38 Hi Marc, On Mon, 24 Aug 2026 17:34:34 +0100, Marc Zyngier wrote: >On Mon, 24 Aug 2026 03:34:03 +0100, >Li Dou wrote: >> >> ARM GICv3 specification says(in section 4.8.4 "System register access to >> the Active Priorities registers"): >> >> an ISB is not required between each write to ICC_AP0R_EL1, >> Secure ICC_AP1R_EL1, and Non-secure ICC_AP1R_EL1. >> >> It means we can use one ISB after resetting AP0Rn and AP1Rn for context >> synchronization. So just remove the previous one. > >I'm afraid you have misinterpreted the spec. > >Within each of the AP0Rn, Secure AP1Rn and Non-Secure AP1Rn classes, >for any value of 'n', there is no need for any synchronisation. > >However, between classes, you absolutely need an ISB. And this is the >reason why, just above the note you quote: > > >Writes to these registers in any order other than the following can >result in UNPREDICTABLE behavior: > >1. ICC_AP0R_EL1. >2. Secure ICC_AP1R_EL1. >3. Non-secure ICC_AP1R_EL1. > > >While you can perfectly write each individual register of (1), (2) or >(3) without any synchronisation, you absolutely must have a CSE >*between* each of (1), (2) and (3). Linux being non-secure only, you >only deal with (1) and (3), and you must have an ISB in between. >Without it, reordering can happen and you end-up violating the above >rule. The spec sometimes is overly convoluted. Thanks for the clarification. Best regards, Li