From: Jason Gunthorpe <jgg@nvidia.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: linux-riscv@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com,
fangyu.yu@linux.alibaba.com
Subject: Re: [PATCH v4 02/21] iommufd: Add iommufd_sw_map_msi()
Date: Tue, 25 Aug 2026 13:52:09 -0300 [thread overview]
Message-ID: <20260825165209.GB3325090@nvidia.com> (raw)
In-Reply-To: <cxbneh42ui3gbkoqrsnoatxoec5exzbprfbgxcy4iekqmbceho@gouiwn5q5uzs>
On Tue, Aug 25, 2026 at 06:14:55PM +0200, Andrew Jones wrote:
> On Tue, Aug 25, 2026 at 11:03:34AM -0300, Jason Gunthorpe wrote:
> > On Tue, Aug 25, 2026 at 03:24:01PM +0200, Andrew Jones wrote:
> >
> > > The irqdomains remain per-device. The MSI table belongs to the
> > > corresponding S2 IOMMU domain and its configuration is bound to one VM's
> > > IMSIC topology. The current prototype rejects irqbypass from another VM
> > > once the table has an owner. The irqdomain does not sit on top of the
> > > vIOMMUs. A vIOMMU links guest-controlled S1 domains to their S2 parent,
> > > while the per-device irqdomain is the IRQ-side entry point for updating
> > > that parent's MSI table.
> >
> > Doesn't sound like the right design to me. Pretending it is not bound
> > to the S2 just to make it global then blocking multi-VM is not a good
> > place to start from.
>
> The MSI table fields are part of the IOMMU device context, and the
> device's irqdomain is how IRQ operations reach the IOMMU driver. The
> table storage is owned by the S2 domain so all devices attached to that
> domain use the same mappings. Sharing an S2 domain between VMs would
> also share their DMA address space, so rejecting a different owner for
> the MSI table is only a sanity check, not an expected limitation.
That's not what I'm saying, having one irqdomain controlling two
msitables based on how the iommu happens to be configured, and what
device the IRQ is is using does not seem like a great arrangement in
general.
We have enough problems keeping the iommu and irq layers in sync, now
this is making them even more split. It makes more sense to me if the
irqdomain has a singular msitable and the iommu progams that into the
device context, not the other way around. This of course implies that
each vm gets its own irqdomain plus table and all its VFIO devices are
joined to it.
This seems broadly similar to the other arches where you do want to
have some kind of per-vm control point that the VFIO devices are
bundled into that programs the remapping HW for that slice of the
system.
IDK what Thomas thinks..
> > And this is an entirely different thing, you don't need a domain just
> > to call irq_compose_msi_msg()..
>
> The IOMMU irqdomain does not merely call irq_compose_msi_msg(). It
> implements that callback to perform host MSI remapping. Without this
> layer, that remapping logic would have to be put in the IMSIC driver,
> where it does not belong.
You've lost me there, the host does not use the msi table so what
remapping logic is there?
Jason
next prev parent reply other threads:[~2026-08-25 16:52 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-20 21:41 [PATCH v4 00/21] iommu/riscv: Enable MSI remapping, IOMMU_DMA and VFIO Andrew Jones
2026-08-20 21:41 ` [PATCH v4 01/21] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Andrew Jones
2026-08-20 21:41 ` [PATCH v4 02/21] iommufd: Add iommufd_sw_map_msi() Andrew Jones
2026-08-20 22:09 ` Jason Gunthorpe
2026-08-21 11:07 ` Andrew Jones
2026-08-21 12:02 ` Jason Gunthorpe
2026-08-21 13:47 ` Andrew Jones
2026-08-21 14:00 ` Jason Gunthorpe
2026-08-21 14:23 ` Andrew Jones
2026-08-21 14:31 ` Jason Gunthorpe
2026-08-21 15:18 ` Andrew Jones
2026-08-21 16:12 ` Jason Gunthorpe
2026-08-21 17:12 ` Andrew Jones
2026-08-21 17:20 ` Jason Gunthorpe
2026-08-22 13:50 ` Andrew Jones
2026-08-22 14:06 ` Jason Gunthorpe
2026-08-24 8:50 ` Andrew Jones
2026-08-24 12:52 ` Jason Gunthorpe
2026-08-24 15:43 ` Andrew Jones
2026-08-24 17:04 ` Jason Gunthorpe
2026-08-25 13:24 ` Andrew Jones
2026-08-25 14:03 ` Jason Gunthorpe
2026-08-25 16:14 ` Andrew Jones
2026-08-25 16:52 ` Jason Gunthorpe [this message]
2026-08-25 17:38 ` Andrew Jones
2026-08-25 17:59 ` Jason Gunthorpe
2026-08-26 8:23 ` Andrew Jones
2026-08-26 14:48 ` Andrew Jones
2026-08-26 16:32 ` Jason Gunthorpe
2026-08-26 18:11 ` Andrew Jones
2026-08-27 8:47 ` Andrew Jones
2026-08-27 12:11 ` Jason Gunthorpe
2026-08-20 21:41 ` [PATCH v4 03/21] iommu/dma: Add iommu_dma_sw_map_msi() Andrew Jones
2026-08-20 21:41 ` [PATCH v4 04/21] iommu/dma: Add iommu_dma_map_msi() Andrew Jones
2026-08-20 21:41 ` [PATCH v4 05/21] iommu: Document MSI mapping during domain replacement Andrew Jones
2026-08-20 21:41 ` [PATCH v4 06/21] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP Andrew Jones
2026-08-20 21:41 ` [PATCH v4 07/21] irqchip/riscv-imsic: Compose MSI updates through the hierarchy Andrew Jones
2026-08-20 21:41 ` [PATCH v4 08/21] iommu/riscv: Add IRQ domain for interrupt remapping Andrew Jones
2026-08-20 21:41 ` [PATCH v4 09/21] iommu/riscv: Refresh platform MSI domain before IR setup Andrew Jones
2026-08-20 21:41 ` [PATCH v4 10/21] iommu/riscv: Prepare info->domain for concurrent RCU read access Andrew Jones
2026-08-20 21:41 ` [PATCH v4 11/21] iommu/riscv: Reserve an MSI IOVA window for iommufd Andrew Jones
2026-08-20 21:41 ` [PATCH v4 12/21] iommu/riscv: Pre-map IMSIC MSI targets Andrew Jones
2026-08-20 21:41 ` [PATCH v4 13/21] iommu/riscv: Preserve MSI IOVA state across domain replacement Andrew Jones
2026-08-20 21:52 ` Jason Gunthorpe
2026-08-21 11:14 ` Andrew Jones
2026-08-21 13:22 ` Jason Gunthorpe
2026-08-21 13:56 ` Andrew Jones
2026-08-20 21:41 ` [PATCH v4 14/21] iommu/riscv: Gate direct identity boundary switches with live MSIs Andrew Jones
2026-08-20 21:41 ` [PATCH v4 15/21] iommu/riscv: Remap IMSIC targets during MSI composition Andrew Jones
2026-08-20 21:41 ` [PATCH v4 16/21] iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V Andrew Jones
2026-08-20 21:41 ` [PATCH v4 17/21] iommu/riscv: Report cache coherency capability Andrew Jones
2026-08-20 21:47 ` Jason Gunthorpe
2026-08-21 11:15 ` Andrew Jones
2026-08-20 21:41 ` [PATCH v4 18/21] vfio: enable IOMMU_TYPE1 for RISC-V Andrew Jones
2026-08-20 21:41 ` [PATCH v4 19/21] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Andrew Jones
2026-08-20 21:41 ` [PATCH v4 20/21] riscv: defconfig: Enable IOMMUFD and VFIO Andrew Jones
2026-08-20 21:41 ` [PATCH v4 21/21] selftests/vfio: Allow building on RISC-V Andrew Jones
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