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Wed, 26 Aug 2026 11:25:53 -0700 (PDT) Received: from fedora ([2404:3100:1006:efb1:8177:ae9d:629e:eab1]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a9b43absm612769666b.51.2026.08.26.11.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 11:25:53 -0700 (PDT) From: Saim Shujah To: Rob Clark , Dmitry Baryshkov Cc: Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Saim Shujah Subject: [PATCH] drm/msm/dpu: clear pending flush state before physical cleanup Date: Wed, 26 Aug 2026 23:24:59 +0500 Message-ID: <20260826182459.1506522-1-saimzst@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hardware can consume an active-frame CTL flush while the cached software pending-flush mask retains the submitted bits. Video-mode disable stops the timing engine before physical cleanup, which then adds teardown bits to the stale cached mask. The teardown trigger can replay source-pipe bits after timing stops, leaving one pending and preventing the first commit after re-enable. Clear the cached pending-flush bookkeeping before constructing the teardown state. clear_pending_flush() updates software bookkeeping only; it does not write the hardware CTL_FLUSH register. Fixes: 22cb02bc96ff ("drm/msm/disp/dpu: reset the datapath after timing engine disable") Cc: stable@vger.kernel.org Signed-off-by: Saim Shujah --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 778e231..f3b1fdc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2264,6 +2264,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) dpu_enc = to_dpu_encoder_virt(phys_enc->parent); + ctl->ops.clear_pending_flush(ctl); ctl->ops.reset(ctl); dpu_encoder_helper_reset_mixers(phys_enc); -- 2.55.0