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[79.26.252.140]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49b465226d8sm50099535e9.0.2026.08.27.05.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 05:21:43 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY Date: Thu, 27 Aug 2026 14:21:20 +0200 Message-ID: <20260827122127.18874-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260827122127.18874-1-ansuelsmth@gmail.com> References: <20260827122127.18874-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document support for AN7583 PCIe PHY used to make the Gen3 PCIe port work. Add the required register to configure the PCIe PHY and provide an example for it. Signed-off-by: Christian Marangi --- .../phy/airoha,an7583-pcie-gen3-phy.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml new file mode 100644 index 000000000000..07bb20152c0a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7583-pcie-gen3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 PCI-Express PHY + +maintainers: + - Christian Marangi + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port. + +properties: + compatible: + const: airoha,an7583-pcie-gen3-phy + + reg: + items: + - description: PCIE G3 analog base address + - description: PCIE G3 PMA base address + - description: PCIE detection time base address + - description: PCIE Rx AEQ base address + + reg-names: + items: + - const: g3-ana + - const: g3-pma + - const: xr-dtime + - const: rx-aeq + + phys: + items: + - description: phandle to QPHY phy for Gen2 support + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - phys + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + phy@1fc7f000 { + compatible = "airoha,an7583-pcie-gen3-phy"; + reg = <0x1fc7f000 0xfff>, + <0x1fc7e000 0xfff>, + <0x1fc30044 0x4>, + <0x1fc35030 0x4>; + reg-names = "g3-ana", "g3-pma", + "xr-dtime", "rx-aeq"; + + phys = <&pcie1_phy PHY_TYPE_PCIE>; + + #phy-cells = <0>; + }; -- 2.53.0