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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b0fd9085sm3245892a91.12.2026.08.27.09.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:08:46 -0700 (PDT) From: Linlin Zhang To: ebiggers@kernel.org, axboe@kernel.dk, mst@redhat.com, jasowangio@gmail.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-block@vger.kernel.org, linux-crypto@vger.kernel.org, linux-scsi@vger.kernel.org, virtualization@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: neeraj.soni@oss.qualcomm.com, gaurav.kashyap@oss.qualcomm.com, mani@kernel.org, andersson@kernel.org, konradybcio@kernel.org, bvanassche@acm.org, alim.akhtar@samsung.com, avri.altman@sandisk.com, stefanha@redhat.com, pbonzini@redhat.com, eperezma@redhat.com, xuanzhuo@linux.alibaba.com, linux-kernel@vger.kernel.org Subject: [PATCH v1 11/11] scsi: ufs: ufs-qcom: support ICE keyslot partitioning for guest VMs Date: Thu, 27 Aug 2026 09:07:20 -0700 Message-ID: <20260827160806.1295313-12-linlin.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260827160806.1295313-1-linlin.zhang@oss.qualcomm.com> References: <20260827160806.1295313-1-linlin.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: fISEa9CiJWpxapbfgsXFCuhUk_TxZNP1 X-Proofpoint-GUID: fISEa9CiJWpxapbfgsXFCuhUk_TxZNP1 X-Authority-Analysis: v=2.4 cv=FpU1OWrq c=1 sm=1 tr=0 ts=6a90610f cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=Ui157SQb00ZPLHfqI5IA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDEzNiBTYWx0ZWRfX9s29tSGaekwC 0DYavBnczHjvFTkOnOMYzalhQO6AaJ8K38ukTNhBeYR9x/xke1e+b5b/sSLXhJ793qjsoCDNYGo UIMfShAArfmFwsNIsAggc1tORkNAWzmU4DznYpw4EKE73fgQoFIvXjPMWaGla3RPnOeKTVp9zg/ fXvUUyqXffRWahxCkygfu/s4FdD4fHpQc43WClb8ARijdN8MwxP5CGAa4AQ45yxxHcXpkrIQwTm THKZe8ib/zNeTqS+JWk617hK9WrwLrqyhB4Aom528KhJYC8cuzzRRVfi5Rd5nEwWd1j8Xgcp+Fp NLTeiq3i/JheytdnUk3W3u/aArNG8JPqx4LXdstLkbHRQ+iO33qTssnUWFNeHrzdN3sz95tZSzB tQ8DZpvCwzR8GFBRcmhuSXBdEIqMJ1xjeNTW3xSbNYftPqHnfrrwlwmw9EA51qTxTRni/cc1QwP IUX3BTFi/qgDeq4J5YQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDEzNiBTYWx0ZWRfX+oKtAlzQNjdT MqKHvQoEh3tUrEvaCpXPZM5DAogh02KDSF6Ed2+qvouCD+b1HaJGs4+xMtvkaZYdhaOIVHyOknd 84FLFMlJSj8Q1pTgMtioOQ+RKnOo/pc= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270136 From: linlzhan On Qualcomm platforms where UFS inline encryption is shared between the host and guest VMs, the ICE hardware keyslots must be partitioned so that each VM operates only within its own physical slot range. Without this, the host's blk_crypto_profile would manage all hardware slots, conflicting with slots already allocated to guests. Add ufs_qcom_ice_parse_slot_table() to read the qcom,ice-keyslot-map device-tree node. The function parses all child entries and validates that no entry's slot range or the combined total exceeds the hardware slot count from REG_UFS_CCAP. The first child entry is taken as the host's own reservation; its slot count and offset are returned to the caller. In ufs_qcom_ice_init(), use the parsed host reservation to initialize the blk_crypto_profile with only the host's slot count rather than the full hardware range. Set profile->slot_offset so that blk_crypto_keyslot_index() returns the correct physical ICE slot number when programming hardware. If no qcom,ice-keyslot-map node is present, the existing behaviour (profile manages all slots) is preserved. Note: This patch is submitted for visibility. The ufs-qcom driver gets its max_slots and slot_offset based on the the current DT-based keyslot mechanis. we are aware this may need to be replaced by a TZ SCM interface, submit it RFC for design discussion. Signed-off-by: linlzhan --- drivers/ufs/host/ufs-qcom.c | 91 ++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 62396212a0a7..0611ab50f4cc 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -163,6 +163,74 @@ static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) qcom_ice_enable(host->ice); } +/** + * ufs_qcom_ice_parse_slot_table() - parse qcom,ice-keyslot-map DT node + * @dev: UFS controller device + * @hw_max_slots: total physical ICE keyslots reported by REG_UFS_CCAP + * @num_slots: receives host max_ice_slots (0 = no partitioning) + * @slot_offset: receives host ice-slot-offset + * + * Parses the qcom,ice-keyslot-map device-tree node. The first child entry + * is the host's own reservation; subsequent children are guest reservations. + * Validates that no entry's range exceeds @hw_max_slots and that the sum of + * all entries does not exceed @hw_max_slots. + * + * If no qcom,ice-keyslot-map phandle is present, sets @num_slots to 0 and + * returns 0. Returns -EINVAL if any entry or the total exceeds @hw_max_slots. + */ +static int ufs_qcom_ice_parse_slot_table(struct device *dev, + unsigned int hw_max_slots, + unsigned int *num_slots, + unsigned int *slot_offset) +{ + struct device_node *slots_np, *child; + unsigned int total_slots = 0; + bool first = true; + int ret = 0; + + *num_slots = 0; + *slot_offset = 0; + + slots_np = of_parse_phandle(dev->of_node, "qcom,ice-keyslot-map", 0); + if (!slots_np) + return 0; + + for_each_child_of_node(slots_np, child) { + u32 off, max; + + if (of_property_read_u32(child, "qcom,ice-slot-offset", &off) || + of_property_read_u32(child, "qcom,max-ice-slots", &max)) + continue; + + if (off + max > hw_max_slots) { + dev_err(dev, + "ice-keyslot-map: slots [%u..%u) exceed hw max %u\n", + off, off + max, hw_max_slots); + of_node_put(child); + ret = -EINVAL; + break; + } + + if (first) { + *num_slots = max; + *slot_offset = off; + first = false; + } + total_slots += max; + } + + of_node_put(slots_np); + + if (!ret && total_slots > hw_max_slots) { + dev_err(dev, + "ice-keyslot-map: total slots %u exceed hw max %u\n", + total_slots, hw_max_slots); + ret = -EINVAL; + } + + return ret; +} + static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */ static int ufs_qcom_ice_init(struct ufs_qcom_host *host) @@ -173,6 +241,8 @@ static int ufs_qcom_ice_init(struct ufs_qcom_host *host) struct qcom_ice *ice; union ufs_crypto_capabilities caps; union ufs_crypto_cap_entry cap; + unsigned int num_slots, slot_offset; + unsigned int hw_max_slots; int err; int i; @@ -192,7 +262,23 @@ static int ufs_qcom_ice_init(struct ufs_qcom_host *host) caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); /* The number of keyslots supported is (CFGC+1) */ - err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1); + hw_max_slots = caps.config_count + 1; + + /* + * Parse the qcom,ice-keyslot-map DT node: validate all entries against + * the hardware slot count and read the host's own reservation. If no + * partitioning is configured (num_slots == 0), the profile manages the + * full hardware slot range. + */ + err = ufs_qcom_ice_parse_slot_table(dev, hw_max_slots, + &num_slots, &slot_offset); + if (err) { + dev_err(dev, "failed to parse ICE slot table: %d\n", err); + return err; + } + + err = devm_blk_crypto_profile_init(dev, profile, + num_slots ? num_slots : hw_max_slots); if (err) return err; @@ -201,6 +287,9 @@ static int ufs_qcom_ice_init(struct ufs_qcom_host *host) profile->key_types_supported = qcom_ice_get_supported_key_type(ice); profile->dev = dev; + if (num_slots) + profile->slot_offset = slot_offset; + /* * Currently this driver only supports AES-256-XTS. All known versions * of ICE support it, but to be safe make sure it is really declared in -- 2.34.1