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Fri, 28 Aug 2026 01:44:10 -0700 (PDT) X-Received: by 2002:a17:903:24f:b0:2cf:c543:2c7e with SMTP id d9443c01a7336-2d74df5fa9dmr90022845ad.10.1787906650197; Fri, 28 Aug 2026 01:44:10 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3286f784857sm3673459eec.3.2026.08.28.01.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 01:44:09 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 28 Aug 2026 14:13:37 +0530 Subject: [PATCH v2 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260828-nord-v2-3-18bf59d19d6f@oss.qualcomm.com> References: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> In-Reply-To: <20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel Cc: Krishna Chaitanya Chundru , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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To avoid the issue, set the CORE_CLK_CGC_DIS and AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization. The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This change adds the remaining required settings as documented in QCTDD11972446. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index b58a607b713f..b97e40fb7ec8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -281,6 +281,7 @@ struct qcom_pcie_cfg { bool override_no_snoop; bool firmware_managed; bool no_l0s; + bool cgc_dis_workaround; }; struct qcom_pcie_perst { @@ -1097,11 +1098,18 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) { const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; + u32 val; if (pcie_cfg->override_no_snoop) writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, pcie->parf + PARF_NO_SNOOP_OVERRIDE); + if (pcie_cfg->cgc_dis_workaround) { + val = readl(pcie->parf + PARF_SYS_CTRL); + val |= CORE_CLK_CGC_DIS | AUX_PWR_DET; + writel(val, pcie->parf + PARF_SYS_CTRL); + } + qcom_pcie_set_slot_cap(pcie->pci); return 0; @@ -1630,6 +1638,13 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { .ops = &ops_2_9_0, }; +static const struct qcom_pcie_cfg cfg_nord = { + .ops = &ops_1_9_0, + .override_no_snoop = true, + .no_l0s = true, + .cgc_dis_workaround = true, +}; + static const struct qcom_pcie_cfg cfg_sc8280xp = { .ops = &ops_1_21_0, .no_l0s = true, @@ -2464,6 +2479,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 }, + { .compatible = "qcom,nord-pcie", .data = &cfg_nord }, { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, -- 2.34.1