From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Changhuang Liang <changhuang.liang@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>
Subject: [PATCH v5 4/8] clk: starfive: Add Peripheral-1 domain PLL clock driver
Date: Fri, 28 Aug 2026 02:56:04 -0700 [thread overview]
Message-ID: <20260828095608.19955-5-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260828095608.19955-1-changhuang.liang@starfivetech.com>
Add Peripheral-1 domain PLL clock driver support for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
.../clk/starfive/clk-starfive-jhb100-pll.c | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
index f6ebaaf5aa18..eb91131857f1 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -33,6 +33,9 @@
/* Peripheral-0 domain PLL */
#define JHB100_PLL6_OFFSET 0x00
+/* Peripheral-1 domain PLL */
+#define JHB100_PLL7_OFFSET 0x40
+
#define JHB100_PLL_CFG0_OFFSET 0x0
#define JHB100_PLL_CFG1_OFFSET 0x4
#define JHB100_PLL_CFG2_OFFSET 0x8
@@ -534,6 +537,28 @@ static const struct jhb100_pll_match_data jhb100_per0_pll = {
.num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
};
+static const struct jhb100_pll_preset jhb100_pll7_presets[] = {
+ {
+ .freq = 1950000000,
+ .fbdiv = 156,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_per1_pll_info[] = {
+ JHB100_PLL(JHB100_PER1PLL_PLL7_OUT, "pll7_out", jhb100_pll7_presets,
+ ARRAY_SIZE(jhb100_pll7_presets), JHB100_PLL7_OFFSET, false),
+};
+
+static const struct jhb100_pll_match_data jhb100_per1_pll = {
+ .pll_info = jhb100_per1_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_per1_pll_info),
+};
+
static const struct platform_device_id jhb100_pll_ids[] = {
{
.name = "jhb100-sys0-pll",
@@ -548,6 +573,10 @@ static const struct of_device_id jhb100_pll_match[] = {
.compatible = "starfive,jhb100-per0-syscon",
.data = &jhb100_per0_pll,
},
+ {
+ .compatible = "starfive,jhb100-per1-syscon",
+ .data = &jhb100_per1_pll,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jhb100_pll_match);
--
2.25.1
next prev parent reply other threads:[~2026-08-28 13:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 9:56 [PATCH v5 0/8] Add StarFive JHB100 syscon modules Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 1/8] dt-bindings: soc: starfive: " Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 2/8] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 3/8] clk: starfive: Add peripheral-0 " Changhuang Liang
2026-08-28 9:56 ` Changhuang Liang [this message]
2026-08-28 9:56 ` [PATCH v5 5/8] reset: starfive: Introduce active_low Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 6/8] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 7/8] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 8/8] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-09-08 20:06 ` [PATCH v5 0/8] Add StarFive JHB100 syscon modules Conor Dooley
2026-09-09 1:06 ` Changhuang Liang
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