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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?9ONqkxFdOgPoy+2lC3FReXoaC6I4TfO9uw861nNDa+WV3Xbl8r19hObWRSEa?= =?us-ascii?Q?Dhx9EJVIEYPplum9pwLSQUYfbxve9ZhD/Ibtfz8R9txXcry9RLv8xuN5BUO1?= =?us-ascii?Q?/xT6PSLmxvOe+hrLd4VrhIl71FzO/wwZ39K++yoXM+ds8hELmKySqILCtED7?= =?us-ascii?Q?lZVuNKD0M2/Ul2G4+PAQnzuUVfLID1vVY1WP7vx6yIVSHOt0eutJycywKvp8?= =?us-ascii?Q?v/T5vQiMAE6P2mpfOl39XuNrUWmHWN7kW60dcGJJJ4LH7Rvp3xJtVa3tc14j?= =?us-ascii?Q?uhkFx5FSrm1TTzZ6nKNbhcXWBgloLdL+xI96PTJovM4EK2s96N6lc25ZH2J3?= =?us-ascii?Q?VXoI4Ni0FTjWs/LpYiQP2K80H65QkOcNLvxWwWvnLf60pTRIOtx20nW60jDF?= =?us-ascii?Q?+trh7CZoLcnfnmo6EaDAtP+bYI/vPEHZOwQW9p/WvZy/K1peE26+HAqmSsgy?= =?us-ascii?Q?mduOjgUelt9lJ8sq43TFO5EZk9jwghmrGwiGTkxtcBvklP+p0DccI8DA/HzM?= =?us-ascii?Q?AuU+Ha9A4kmmGhKFyeXW+Bn5g9Yr0U4VZilkBw8PkMaEuSmqIG+sifbuLaMD?= =?us-ascii?Q?Bt4sdKWt9QHblQ+DDtpo8pLnEd6Xhqi65WC+0B22c+Wi272ighpvjAqCrscO?= =?us-ascii?Q?bAeuRhU3uijgZVXvOFrRwZjCu31r8snZRkeTcGiE0HQH0PHRyq6yU9jiTdiZ?= =?us-ascii?Q?5lzcf4ZxB5zT4qYWN/kxES4XDdjLC2U2I8rra3u7/kPPMH6gfW/d44snQ6j4?= =?us-ascii?Q?cYsLT1V5cauyxw+/pDOacyyFsNQMaWrLhwsZzXT1j41/k7yqisd4Hc7+VQet?= =?us-ascii?Q?6bXtj7H2VrlhMcOkIpNL1kl06cJy4tyPjnZnnXOwY9Oi5WyRggKZvgolSGKt?= =?us-ascii?Q?Rfou5JFCmN6HUOsb76C77xrOS5QEldLN2dkjCdXOGp8V1o3Ewx/YEko9F5LT?= =?us-ascii?Q?Lv/VoZsbOUrgr79miw0kL9Pa8lYp6K5fwSxILeDV4n4i5R5zL3FbqeiR4Inf?= =?us-ascii?Q?ufJMTVcqHTj28fHKu33BNu2Au+Q9AuWN3ioSmfuonNVA0Rh8cEL8XZ4aA7Tt?= =?us-ascii?Q?J49WRY0iCUPdsnok7EMNJK3zK9kUELuSNCQGx3j6NfxMwozVFLcaUgC/f3Cd?= =?us-ascii?Q?wr4u0pwuHz6IYjtPfCv5gEXIZyXdoqG54+WLcE9taHTQctcxx75E9bCDjD+r?= =?us-ascii?Q?2b3v5DB1ckVO8LkUCFidF95e1F7RsVgNLPC9gacKgsUK+zmncTpQjDSxnPLj?= =?us-ascii?Q?WDahCyDNSB5gsjxS6trmwKt/s26ZK4nxfRwgCEUx/pwH99VNmIyPRSFe/5ft?= =?us-ascii?Q?kh4EYa5yuoVgilv6HX3ZL9rnPQF8+mZ0jZ41ECLsPc8cxDHNKTSjOhj+PFTa?= =?us-ascii?Q?IvWM0VPSH+1DmRIE2LCgZ+RNZu1UT+Kr5wFxR87RSOWKY9/Y+smMIOWQYINk?= =?us-ascii?Q?bOr5FoHOGufin1z9NJx2ReM5ELa3JTCqqic8H87iVW62Li7LX3nO/Mr/kYf1?= =?us-ascii?Q?rV2irq5E5ShehtV5EGua+142TprKuxylLgWjPI1VblAai5ImY4sBYvHGCOXA?= =?us-ascii?Q?7CdeohE6Q4IRpf/zUeVtNOpRQz1+87npIK0hWxtCc1lGBK/Ig9GsdBKvFPxp?= =?us-ascii?Q?48VS/K+IH84MtlQrth30Aq0KCU3Oh67O6gHbopIRxKRo4x9CO7X40kRV35F4?= =?us-ascii?Q?KdVCHA/GZeWxME5FT8kzEe7Qq32yfQNTb0Oi4WB31CctYI47mTGMwtuWton7?= =?us-ascii?Q?6KdEu+/ysA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0cb4cb09-6473-4d12-f2c0-08df056c0cf2 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2026 01:22:54.3240 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2+0IlvAWm7lsWRQUDwCPSli+bMj/sZR/4TO26mcabZWiB3iZm0qKMD+LyzsR3eZ7CzcT3T3HJjkznrvTDSWXiA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6125 GIN, the GPU Interrupt and Notification unit, is the GPU's interrupt controller. Each PCIe function has its own tree, whose leaf count depends on the GPU family. Message-signaled delivery stops after each edge until the CPU rearms it, and the rearm write differs by family and interrupt type: * Pre-Hopper MSI writes an EOI through the BAR0 PCI configuration space mirror. * MSI for Hopper and later cycles the TOP enable bits of every serviced subtree. * MSI-X on any family cycles the bits of the handler's own subtree. Provide the leaf count and the rearm method through a per-architecture interrupt HAL. Assisted-by: Cursor:claude-opus-5 Reviewed-by: Will Pierce Signed-off-by: John Hubbard --- drivers/gpu/nova-core/irq.rs | 1 + drivers/gpu/nova-core/irq/hal.rs | 111 +++++++++++++++++++++++++ drivers/gpu/nova-core/irq/hal/gh100.rs | 31 +++++++ drivers/gpu/nova-core/irq/hal/tu102.rs | 30 +++++++ 4 files changed, 173 insertions(+) create mode 100644 drivers/gpu/nova-core/irq/hal.rs create mode 100644 drivers/gpu/nova-core/irq/hal/gh100.rs create mode 100644 drivers/gpu/nova-core/irq/hal/tu102.rs diff --git a/drivers/gpu/nova-core/irq.rs b/drivers/gpu/nova-core/irq.rs index 3066ceeb850c..02ecfc47f4d0 100644 --- a/drivers/gpu/nova-core/irq.rs +++ b/drivers/gpu/nova-core/irq.rs @@ -8,5 +8,6 @@ //! //! See `Documentation/gpu/nova/core/interrupts.rst`. +mod hal; mod interrupt_tree; mod regs; diff --git a/drivers/gpu/nova-core/irq/hal.rs b/drivers/gpu/nova-core/irq/hal.rs new file mode 100644 index 000000000000..ee354859b965 --- /dev/null +++ b/drivers/gpu/nova-core/irq/hal.rs @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +//! Per-architecture properties of the GIN CPU interrupt tree. + +mod gh100; +mod tu102; + +use kernel::{ + io::Io, + pci::IrqType, // +}; + +use crate::{ + driver::Bar0, + gpu::{ + Architecture, + Chipset, // + }, // +}; + +use super::{ + interrupt_tree::{ + LeafCount, + Subtree, + SubtreeSet, // + }, + regs, // +}; + +/// Register write that restores PCI interrupt delivery to the CPU. +/// +/// A message-signaled interrupt is delivered once per edge, and the PCI side delivers no further +/// interrupt until the CPU rearms it. A handler that returns without this write receives no more +/// interrupts. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub(super) enum PciIrqRearmMethod { + /// The MSI end-of-interrupt register in the BAR0 PCI configuration-space mirror, used by + /// MSI on pre-Hopper GPUs. + ConfigMirrorEoi, + + /// A clear then a set of the `TOP` enable bits of every serviced subtree, which produces the + /// edge that delivers the next interrupt. + /// + /// MSI has a single message that every subtree raises, so the rearm covers the whole serviced + /// set. + TopEnableCycleServiced, + + /// The same enable cycle, restricted to the one subtree the handler serves. + /// + /// MSI-X gives each subtree its own table entry and its own handler. + TopEnableCycleSubtree, +} + +impl PciIrqRearmMethod { + /// Performs this method's register write. + /// + /// `serviced` holds every subtree the driver services, and `subtree` is the one subtree the + /// calling handler serves. Each method uses whichever of the two its interrupt type delivers + /// on, so both are required. + pub(super) fn rearm(self, bar: Bar0<'_>, serviced: SubtreeSet, subtree: Subtree) { + let subtrees = match self { + // The written value is ignored, so any write rearms delivery. + Self::ConfigMirrorEoi => { + bar.write(regs::NV_XVE_CYA_2, 0u32.into()); + return; + } + Self::TopEnableCycleServiced => serviced, + Self::TopEnableCycleSubtree => SubtreeSet::from(subtree), + }; + + bar.write( + regs::NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR, + subtrees.into_raw().into(), + ); + bar.write( + regs::NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET, + subtrees.into_raw().into(), + ); + } +} + +/// Per-architecture properties of the GIN CPU interrupt tree. +/// +/// The tree size and the method that rearms PCI interrupt delivery differ by family. The tree +/// walk, the vector encoding, and the read-and-clear sequence do not, and are in generic code. +/// +/// See `Documentation/gpu/nova/core/interrupts.rst`. +pub(super) trait CpuInterruptHal { + /// Returns the number of leaves the CPU tree implements. + /// + /// [`LeafCount::subtree_set`] gives the subtrees behind them, and + /// [`LeafCount::vector_count`] the vectors they carry. + fn leaf_count(&self) -> LeafCount; + + /// Returns the method that rearms PCI interrupt delivery for `irq_type`. + /// + /// `None` means that `irq_type` needs no rearm write. That is the case for `INTx`, which is + /// level-triggered, and which nova-core does not allocate. + fn pci_irq_rearm_method(&self, irq_type: IrqType) -> Option; +} + +/// Returns the [`CpuInterruptHal`] for `chipset`. +pub(super) fn cpu_interrupt_hal(chipset: Chipset) -> &'static dyn CpuInterruptHal { + match chipset.arch() { + Architecture::Turing | Architecture::Ampere | Architecture::Ada => tu102::TU102_HAL, + Architecture::Hopper | Architecture::BlackwellGB10x | Architecture::BlackwellGB20x => { + gh100::GH100_HAL + } + } +} diff --git a/drivers/gpu/nova-core/irq/hal/gh100.rs b/drivers/gpu/nova-core/irq/hal/gh100.rs new file mode 100644 index 000000000000..32b9b4a01adb --- /dev/null +++ b/drivers/gpu/nova-core/irq/hal/gh100.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +use kernel::pci::IrqType; + +use super::{ + CpuInterruptHal, + LeafCount, + PciIrqRearmMethod, // +}; + +/// GIN parameters for Hopper and Blackwell, which implement a 16-leaf CPU tree. Only 12 leaves +/// carry sources. +struct Gh100; + +impl CpuInterruptHal for Gh100 { + fn leaf_count(&self) -> LeafCount { + LeafCount::Sixteen + } + + fn pci_irq_rearm_method(&self, irq_type: IrqType) -> Option { + match irq_type { + IrqType::Intx => None, + IrqType::Msi => Some(PciIrqRearmMethod::TopEnableCycleServiced), + IrqType::MsiX => Some(PciIrqRearmMethod::TopEnableCycleSubtree), + } + } +} + +const GH100: Gh100 = Gh100; +pub(super) const GH100_HAL: &dyn CpuInterruptHal = &GH100; diff --git a/drivers/gpu/nova-core/irq/hal/tu102.rs b/drivers/gpu/nova-core/irq/hal/tu102.rs new file mode 100644 index 000000000000..e22eb37906a8 --- /dev/null +++ b/drivers/gpu/nova-core/irq/hal/tu102.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +use kernel::pci::IrqType; + +use super::{ + CpuInterruptHal, + LeafCount, + PciIrqRearmMethod, // +}; + +/// GIN parameters for Turing, Ampere, and Ada, which implement an 8-leaf CPU tree. +struct Tu102; + +impl CpuInterruptHal for Tu102 { + fn leaf_count(&self) -> LeafCount { + LeafCount::Eight + } + + fn pci_irq_rearm_method(&self, irq_type: IrqType) -> Option { + match irq_type { + IrqType::Intx => None, + IrqType::Msi => Some(PciIrqRearmMethod::ConfigMirrorEoi), + IrqType::MsiX => Some(PciIrqRearmMethod::TopEnableCycleSubtree), + } + } +} + +const TU102: Tu102 = Tu102; +pub(super) const TU102_HAL: &dyn CpuInterruptHal = &TU102; -- 2.55.0