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Sat, 29 Aug 2026 02:57:54 +0000 From: Changhuang Liang To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Albert Ou , Palmer Dabbelt , Alexandre Ghiti , Philipp Zabel , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Lianfeng Ouyang , Changhuang Liang Subject: [PATCH v6 15/21] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Date: Fri, 28 Aug 2026 19:57:14 -0700 Message-Id: <20260829025720.23915-16-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260829025720.23915-1-changhuang.liang@starfivetech.com> References: <20260829025720.23915-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn (10.2.8.16) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (10.2.3.102) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1153:EE_ X-MS-Office365-Filtering-Correlation-Id: 9004e4f4-4cdd-484a-1817-08df0579524e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|23010399003|7416014|376014|52116014|3023799007|18002099003|22082099003|56012099006|6133799003|10067099003|921020|38350700014; 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On the StarFive JHB100 SoC, every 32 GPIOs correspond to one register address. Therefore, under this model, every 32 GPIOs can be regarded as one GPIO instance. In this case, the following new approach can be used to represent this model: gpios = <&gpio [instance] offset flags>; gpio-ranges = <&pinctrl [gpio_instance] gpio_offset pin_offset count>; At the same time, this model also reduces the /32 and %32 operations in the driver. Signed-off-by: Changhuang Liang --- .../pinctrl/starfive,jhb100-per2-pinctrl.yaml | 168 ++++++++++++++++++ .../pinctrl/starfive,jhb100-pinctrl.h | 33 ++++ 2 files changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml new file mode 100644 index 000000000000..2df36903be2d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-2 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "per2" pinctrl domain. + + The "per2" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the Peripheral-2 Pin Controller, there are 31 multi-function GPIO_PADs. + Each of them can be multiplexed to several peripherals through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function which is generally the GPIO function. + Function 1, 2, and 3 are the alternate functions or peripheral signals + that can be routed to an iopad. The function selection can be carried + out by writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-per2-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + + gpio-controller: true + + '#gpio-cells': + const: 3 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ fan_tach, gmac_rgmii, gmac_rmii, gpio, host0_port80, + host1_port80 ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 2500, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_per2: pinctrl@11bc2000 { + compatible = "starfive,jhb100-per2-pinctrl"; + reg = <0x0 0x11bc2000 0x0 0x400>; + resets = <&per2crg 0>; + interrupts = <62>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_per2 0 0 0 31>; + }; + }; diff --git a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h index 9f622468c294..2d5150e3adb7 100644 --- a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h @@ -177,4 +177,37 @@ #define PADNUM_PER1_GPIO_C34 34 #define PADNUM_PER1_GPIO_C35 35 +/* per2 pad numbers */ +#define PADNUM_PER2_GPIO_D0 0 +#define PADNUM_PER2_GPIO_D1 1 +#define PADNUM_PER2_GPIO_D2 2 +#define PADNUM_PER2_GPIO_D3 3 +#define PADNUM_PER2_GPIO_D4 4 +#define PADNUM_PER2_GPIO_D5 5 +#define PADNUM_PER2_GPIO_D6 6 +#define PADNUM_PER2_GPIO_D7 7 +#define PADNUM_PER2_GPIO_D8 8 +#define PADNUM_PER2_GPIO_D9 9 +#define PADNUM_PER2_GPIO_D10 10 +#define PADNUM_PER2_GPIO_D11 11 +#define PADNUM_PER2_GPIO_D12 12 +#define PADNUM_PER2_GPIO_D13 13 +#define PADNUM_PER2_GPIO_D14 14 +#define PADNUM_PER2_GPIO_D15 15 +#define PADNUM_PER2_GPIO_D16 16 +#define PADNUM_PER2_GPIO_D17 17 +#define PADNUM_PER2_GPIO_D18 18 +#define PADNUM_PER2_GPIO_D19 19 +#define PADNUM_PER2_GPIO_D20 20 +#define PADNUM_PER2_GPIO_D21 21 +#define PADNUM_PER2_GPIO_D22 22 +#define PADNUM_PER2_GPIO_D23 23 +#define PADNUM_PER2_GPIO_D24 24 +#define PADNUM_PER2_GPIO_D25 25 +#define PADNUM_PER2_GPIO_D26 26 +#define PADNUM_PER2_GPIO_D27 27 +#define PADNUM_PER2_GPIO_D28 28 +#define PADNUM_PER2_GPIO_D29 29 +#define PADNUM_PER2_GPIO_D30 30 + #endif -- 2.25.1